모두의 코드
CVTTSD2SI (Intel x86/64 assembly instruction)
CVTTSD2SI
Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed Integer
참고 사항
아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.
Opcode/ | Op / | 64/32 | CPUID | Description |
|---|---|---|---|---|
| RM | V/V | SSE2 | Convert one double-precision floating-point value from xmm1/m64 to one signed doubleword integer in r32 using truncation. |
| RM | V/N.E. | SSE2 | Convert one double-precision floating-point value from xmm1/m64 to one signed quadword integer in r64 using truncation. |
| RM | V/V | AVX | Convert one double-precision floating-point value from xmm1/m64 to one signed doubleword integer in r32 using truncation. |
| T1F | V/N.E.1 | AVX | Convert one double-precision floating-point value from xmm1/m64 to one signed quadword integer in r64 using truncation. |
| T1F | V/V | AVX512F | Convert one double-precision floating-point value from xmm1/m64 to one signed doubleword integer in r32 using truncation. |
| T1F | V/N.E.1 | AVX512F | Convert one double-precision floating-point value from xmm1/m64 to one signed quadword integer in r64 using truncation. |
For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 ver-sion is used
Instruction Operand Encoding
Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|
RM | ModRM:reg (w) | ModRM:r/m (r) | NA | NA |
T1F | ModRM:reg (w) | ModRM:r/m (r) | NA | NA |
Description
Converts a double-precision floating-point value in the source operand (the second operand) to a signed double-word integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand). The source operand can be an XMM register or a 64-bit memory location. The destination operand is a general purpose register. When the source operand is an XMM register, the double-precision floating-point value is contained in the low quadword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.
If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.
If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (8000000000000000H) is returned.
Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation. See the summary chart at the beginning of this section for encoding data and limits.
VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCVTTSD2SI is encoded with VEX.L=0. Encoding VCVTTSD2SI with VEX.L=1 may encounter unpredictable behavior across different processor generations.
Operation
(V)CVTTSD2SI (All versions)
IF 64-Bit Mode and OperandSize = 64
THEN
DEST[63:0] <- Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0]);
ELSE
DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0]);
FI;
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTSD2SI int _mm_cvttsd_i32(__m128d a); VCVTTSD2SI int _mm_cvtt_roundsd_i32(__m128d a, int sae); VCVTTSD2SI __int64 _mm_cvttsd_i64(__m128d a); VCVTTSD2SI __int64 _mm_cvtt_roundsd_i64(__m128d a, int sae); CVTTSD2SI int _mm_cvttsd_si32(__m128d a); CVTTSD2SI __int64 _mm_cvttsd_si64(__m128d a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3; additionally
#UD If VEX.vvvv != 1111B.
EVEX-encoded instructions, see Exceptions Type E3NF.
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