모두의 코드
DIVSS (Intel x86/64 assembly instruction)
DIVSS
Divide Scalar Single-Precision Floating-Point Values
참고 사항
아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.
Opcode/ | Op / | 64/32 | CPUID | Description |
---|---|---|---|---|
| RM | V/V | SSE | Divide low single-precision floating-point value in xmm1 by low single-precision floating-point value in xmm2/m32. |
| RVM | V/V | AVX | Divide low single-precision floating-point value in xmm2 by low single-precision floating-point value in xmm3/m32. |
| T1S | V/V | AVX512F | Divide low single-precision floating-point value in xmm2 by low single-precision floating-point value in xmm3/m32. |
Instruction Operand Encoding
Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
---|---|---|---|---|
RM | ModRM:reg (r, w) | ModRM:r/m (r) | NA | NA |
RVM | ModRM:reg (w) | VEX.vvvv | ModRM:r/m (r) | NA |
T1S | ModRM:reg (w) | EVEX.vvvv | ModRM:r/m (r) | NA |
Description
Divides the low single-precision floating-point value in the first source operand by the low single-precision floating-point value in the second source operand, and stores the single-precision floating-point result in the destination operand. The second source operand can be an XMM register or a 32-bit memory location.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAXVL-1:32) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The three high-order doublewords of the destination operand are copied from the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.
EVEX.128 encoded version: The first source operand is an xmm register encoded by EVEX.vvvv. The doubleword elements of the destination operand at bits 127:32 are copied from the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.
EVEX version: The low doubleword element of the destination is updated according to the writemask.
Software should ensure VDIVSS is encoded with VEX.L=0. Encoding VDIVSS with VEX.L=1 may encounter unpre-dictable behavior across different processor generations.
Operation
VDIVSS (EVEX encoded version)
IF (EVEX.b = 1) AND SRC2 *is a register* THEN SET_RM(EVEX.RC); ELSE SET_RM(MXCSR.RM); FI; IF k1[0] or *no writemask* THEN DEST[31:0] <- SRC1[31:0] / SRC2[31:0] ELSE IF *merging-masking* ; merging-masking THEN *DEST[31:0] remains unchanged* ELSE ; zeroing-masking THEN DEST[31:0] <- 0 FI; FI; DEST[127:32] <- SRC1[127:32] DEST[MAX_VL-1:128] <- 0
VDIVSS (VEX.128 encoded version)
DEST[31:0] <- SRC1[31:0] / SRC2[31:0] DEST[127:32] <- SRC1[127:32] DEST[MAX_VL-1:128] <- 0
DIVSS (128-bit Legacy SSE version)
DEST[31:0] <- DEST[31:0] / SRC[31:0] DEST[MAX_VL-1:32] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VDIVSS __m128 _mm_mask_div_ss(__m128 s, __mmask8 k, __m128 a, __m128 b); VDIVSS __m128 _mm_maskz_div_ss(__mmask8 k, __m128 a, __m128 b); VDIVSS __m128 _mm_div_round_ss(__m128 a, __m128 b, int); VDIVSS __m128 _mm_mask_div_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int); VDIVSS __m128 _mm_maskz_div_round_ss(__mmask8 k, __m128 a, __m128 b, int); DIVSS __m128 _mm_div_ss(__m128 a, __m128 b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.
댓글을 불러오는 중입니다..