모두의 코드
HADDPS (Intel x86/64 assembly instruction)

작성일 : 2020-09-01 이 글은 893 번 읽혔습니다.

HADDPS

Packed Single-FP Horizontal Add

참고 사항

아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.

Opcode/
Instruction

Op/
En

64/32-bit
Mode

CPUID
Feature
Flag

Description

F2 0F 7C /r
HADDPS xmm1 xmm2/m128

RM

V/V

SSE3

Horizontal add packed single-precision floating-point values from xmm2/m128 to xmm1.

VEX.NDS.128.F2.0F.WIG 7C /r
VHADDPS xmm1 xmm2 xmm3/m128

RVM

V/V

AVX

Horizontal add packed single-precision floating-point values from xmm2 and xmm3/mem.

VEX.NDS.256.F2.0F.WIG 7C /r
VHADDPS ymm1 ymm2 ymm3/m256

RVM

V/V

AVX

Horizontal add packed single-precision floating-point values from ymm2 and ymm3/mem.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (r, w)

ModRM:r/m (r)

NA

NA

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

NA

Description

Adds the single-precision floating-point values in the first and second dwords of the destination operand and stores the result in the first dword of the destination operand.

Adds single-precision floating-point values in the third and fourth dword of the destination operand and stores the result in the second dword of the destination operand.

Adds single-precision floating-point values in the first and second dword of the source operand and stores the result in the third dword of the destination operand.

Adds single-precision floating-point values in the third and fourth dword of the source operand and stores the result in the fourth dword of the destination operand.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

See Figure 3-18 for HADDPS; see Figure 3-19 for VHADDPS.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.

VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register.

] : 7 6 : 5 9 ] 4 : 5 9 [ 9 : 2 1 ] 7 2 1 6 9 : 9 m / 5 E 4 [ 3 m : x x : 2 5 [ x : [ 9 [ 1 1 m 6 / m m L m 7 D 3 [ [ 3 [ 1 [ 3 0 1 ] O 1 6 8 3 2 ] m 6 ] ] ] S 1 [ ] ] ] 2 4 2 m [ 2 : + m m 2 m 9 7 / [ ] 1 x : m 1 [ x 3 6 T 1 + : 0 2 ] m m x m 5 M 6 6 2 8 9 2 1 3 : [ 3 P 0 2 ] [ 8 7 : / 4 6 9 H 3 A D x m x [ m , m x 2 1 9 m + 1 R 1 S U : x m 2 m ] 1 3 1 1 3 9 1 0 m [ 1 : 4 x m 1 1 2 9 3 : 2 2 ] ] 3 : : x m m 1 6 3 m 2 / m 1 m [ : 6 0 ] [ x m ] ] m 2 2 6 8 6 : 3 2 5 : 6 / 8 [ 6 4 + m m 2 8
Figure 3-18. HADDPS--Packed Single-FP Horizontal Add

Y + 0 Y 5 X 4 5 Y Y 1 X 0 X 7 Y 5 Y 4 Y 3 Y 2 Y Y X X X X 3 2 X X 2 R S 0 X C S T S E D 3 2 X Y 2 7 X + 6 X 7 Y + 4 1 1 1 Y + + 3 C X X + Y 0 Y 4 1 X + Y 7 6 6 6 + R 5
Figure 3-19. VHADDPS operation

Operation

HADDPS (128-bit Legacy SSE version)

DEST[31:0] <-  SRC1[63:32] + SRC1[31:0]
DEST[63:32] <-  SRC1[127:96] + SRC1[95:64]
DEST[95:64] <-  SRC2[63:32] + SRC2[31:0]
DEST[127:96] <-  SRC2[127:96] + SRC2[95:64] 
DEST[VLMAX-1:128] (Unmodified)

VHADDPS (VEX.128 encoded version)

DEST[31:0] <-  SRC1[63:32] + SRC1[31:0]
DEST[63:32] <-  SRC1[127:96] + SRC1[95:64]
DEST[95:64] <-  SRC2[63:32] + SRC2[31:0]
DEST[127:96] <-  SRC2[127:96] + SRC2[95:64] 
DEST[VLMAX-1:128] <-  0

VHADDPS (VEX.256 encoded version)

DEST[31:0] <-  SRC1[63:32] + SRC1[31:0]
DEST[63:32] <-  SRC1[127:96] + SRC1[95:64]
DEST[95:64] <-  SRC2[63:32] + SRC2[31:0]
DEST[127:96] <-  SRC2[127:96] + SRC2[95:64] 
DEST[159:128] <-  SRC1[191:160] + SRC1[159:128]
DEST[191:160] <-  SRC1[255:224] + SRC1[223:192]
DEST[223:192] <-  SRC2[191:160] + SRC2[159:128]
DEST[255:224] <-  SRC2[255:224] + SRC2[223:192]

Intel C/C++ Compiler Intrinsic Equivalent

HADDPS : __m128 _mm_hadd_ps(__m128 a, __m128 b);
VHADDPS : __m256 _mm256_hadd_ps(__m256 a, __m256 b);

Exceptions

When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.

Numeric Exceptions

Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions

See Exceptions Type 2.

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