모두의 코드
Jcc (Intel x86/64 assembly instruction)

작성일 : 2020-09-01 이 글은 40 번 읽혔습니다.

Jcc

Jump if Condition Is Met

참고 사항

아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.

OpcodeInstructionOp/
En
64-Bit
Mode
Compat/
Leg Mode
Description
77 cbJA rel8DValidValidJump short if above (CF=0 and ZF=0).
73 cbJAE rel8DValidValidJump short if above or equal (CF=0).
72 cbJB rel8DValidValidJump short if below (CF=1).
76 cbJBE rel8DValidValidJump short if below or equal (CF=1 or ZF=1).
72 cbJC rel8DValidValidJump short if carry (CF=1).
E3 cbJCXZ rel8DN.E.ValidJump short if CX register is 0.
E3 cbJECXZ rel8DValidValidJump short if ECX register is 0.
E3 cbJRCXZ rel8DValidN.E.Jump short if RCX register is 0.
74 cbJE rel8DValidValidJump short if equal (ZF=1).
7F cbJG rel8DValidValidJump short if greater (ZF=0 and SF=OF).
7D cbJGE rel8DValidValidJump short if greater or equal (SF=OF).
7C cbJL rel8DValidValidJump short if less (SF!= OF).
7E cbJLE rel8DValidValidJump short if less or equal (ZF=1 or SF!= OF).
76 cbJNA rel8DValidValidJump short if not above (CF=1 or ZF=1).
72 cbJNAE rel8DValidValidJump short if not above or equal (CF=1).
73 cbJNB rel8DValidValidJump short if not below (CF=0).
77 cbJNBE rel8DValidValidJump short if not below or equal (CF=0 and ZF=0).
73 cbJNC rel8DValidValidJump short if not carry (CF=0).
75 cbJNE rel8DValidValidJump short if not equal (ZF=0).
7E cbJNG rel8DValidValidJump short if not greater (ZF=1 or SF!= OF).
7C cbJNGE rel8DValidValidJump short if not greater or equal (SF!= OF).
7D cbJNL rel8DValidValidJump short if not less (SF=OF).
7F cbJNLE rel8DValidValidJump short if not less or equal (ZF=0 and SF=OF).
71 cbJNO rel8DValidValidJump short if not overflow (OF=0).
7B cbJNP rel8DValidValidJump short if not parity (PF=0).
79 cbJNS rel8DValidValidJump short if not sign (SF=0).
75 cbJNZ rel8DValidValidJump short if not zero (ZF=0).
70 cbJO rel8DValidValidJump short if overflow (OF=1).
7A cbJP rel8DValidValidJump short if parity (PF=1).
7A cbJPE rel8DValidValidJump short if parity even (PF=1).
7B cbJPO rel8DValidValidJump short if parity odd (PF=0).
78 cbJS rel8DValidValidJump short if sign (SF=1).
74 cbJZ rel8DValidValidJump short if zero (ZF = 1).
0F 87 cwJA rel16DN.S.ValidJump near if above (CF=0 and ZF=0). Not supported in 64-bit mode.
0F 87 cdJA rel32DValidValidJump near if above (CF=0 and ZF=0).
0F 83 cwJAE rel16DN.S.ValidJump near if above or equal (CF=0). Not supported in 64-bit mode.
OpcodeInstructionOp/
En
64-Bit
Mode
Compat/
Leg Mode
Description
------------------------------------------------------------------------------------------------------------------------------
0F 83 cdJAE rel32DValidValidJump near if above or equal (CF=0).
0F 82 cwJB rel16DN.S.ValidJump near if below (CF=1). Not supported in 64-bit mode.
0F 82 cdJB rel32DValidValidJump near if below (CF=1).
0F 86 cwJBE rel16DN.S.ValidJump near if below or equal (CF=1 or ZF=1). Not supported in 64-bit mode.
0F 86 cdJBE rel32DValidValidJump near if below or equal (CF=1 or ZF=1).
0F 82 cwJC rel16DN.S.ValidJump near if carry (CF=1). Not supported in 64-bit mode.
0F 82 cdJC rel32DValidValidJump near if carry (CF=1).
0F 84 cwJE rel16DN.S.ValidJump near if equal (ZF=1). Not supported in 64-bit mode.
0F 84 cdJE rel32DValidValidJump near if equal (ZF=1).
0F 84 cwJZ rel16DN.S.ValidJump near if 0 (ZF=1). Not supported in 64-bit mode.
0F 84 cdJZ rel32DValidValidJump near if 0 (ZF=1).
0F 8F cwJG rel16DN.S.ValidJump near if greater (ZF=0 and SF=OF). Not supported in 64-bit mode.
0F 8F cdJG rel32DValidValidJump near if greater (ZF=0 and SF=OF).
0F 8D cwJGE rel16DN.S.ValidJump near if greater or equal (SF=OF). Not supported in 64-bit mode.
0F 8D cdJGE rel32DValidValidJump near if greater or equal (SF=OF).
0F 8C cwJL rel16DN.S.ValidJump near if less (SF!= OF). Not supported in 64-bit mode.
0F 8C cdJL rel32DValidValidJump near if less (SF!= OF).
0F 8E cwJLE rel16DN.S.ValidJump near if less or equal (ZF=1 or SF!= OF). Not supported in 64-bit mode.
0F 8E cdJLE rel32DValidValidJump near if less or equal (ZF=1 or SF!= OF).
0F 86 cwJNA rel16DN.S.ValidJump near if not above (CF=1 or ZF=1). Not supported in 64-bit mode.
0F 86 cdJNA rel32DValidValidJump near if not above (CF=1 or ZF=1).
0F 82 cwJNAE rel16DN.S.ValidJump near if not above or equal (CF=1). Not supported in 64-bit mode.
0F 82 cdJNAE rel32DValidValidJump near if not above or equal (CF=1).
0F 83 cwJNB rel16DN.S.ValidJump near if not below (CF=0). Not supported in 64-bit mode.
0F 83 cdJNB rel32DValidValidJump near if not below (CF=0).
0F 87 cwJNBE rel16DN.S.ValidJump near if not below or equal (CF=0 and ZF=0). Not supported in 64-bit mode.
0F 87 cdJNBE rel32DValidValidJump near if not below or equal (CF=0 and ZF=0).
0F 83 cwJNC rel16DN.S.ValidJump near if not carry (CF=0). Not supported in 64-bit mode.
0F 83 cdJNC rel32DValidValidJump near if not carry (CF=0).
OpcodeInstructionOp/
En
64-Bit
Mode
Compat/
Leg Mode
Description
------------------------------------------------------------------------------------------------------------------------------
0F 85 cwJNE rel16DN.S.ValidJump near if not equal (ZF=0). Not supported in 64-bit mode.
0F 85 cdJNE rel32DValidValidJump near if not equal (ZF=0).
0F 8E cwJNG rel16DN.S.ValidJump near if not greater (ZF=1 or SF!= OF). Not supported in 64-bit mode.
0F 8E cdJNG rel32DValidValidJump near if not greater (ZF=1 or SF!= OF).
0F 8C cwJNGE rel16DN.S.ValidJump near if not greater or equal (SF!= OF). Not supported in 64-bit mode.
0F 8C cdJNGE rel32DValidValidJump near if not greater or equal (SF!= OF).
0F 8D cwJNL rel16DN.S.ValidJump near if not less (SF=OF). Not supported in 64-bit mode.
0F 8D cdJNL rel32DValidValidJump near if not less (SF=OF).
0F 8F cwJNLE rel16DN.S.ValidJump near if not less or equal (ZF=0 and SF=OF). Not supported in 64-bit mode.
0F 8F cdJNLE rel32DValidValidJump near if not less or equal (ZF=0 and SF=OF).
0F 81 cwJNO rel16DN.S.ValidJump near if not overflow (OF=0). Not supported in 64-bit mode.
0F 81 cdJNO rel32DValidValidJump near if not overflow (OF=0).
0F 8B cwJNP rel16DN.S.ValidJump near if not parity (PF=0). Not supported in 64-bit mode.
0F 8B cdJNP rel32DValidValidJump near if not parity (PF=0).
0F 89 cwJNS rel16DN.S.ValidJump near if not sign (SF=0). Not supported in 64-bit mode.
0F 89 cdJNS rel32DValidValidJump near if not sign (SF=0).
0F 85 cwJNZ rel16DN.S.ValidJump near if not zero (ZF=0). Not supported in 64-bit mode.
0F 85 cdJNZ rel32DValidValidJump near if not zero (ZF=0).
0F 80 cwJO rel16DN.S.ValidJump near if overflow (OF=1). Not supported in 64-bit mode.
0F 80 cdJO rel32DValidValidJump near if overflow (OF=1).
0F 8A cwJP rel16DN.S.ValidJump near if parity (PF=1). Not supported in 64-bit mode.
0F 8A cdJP rel32DValidValidJump near if parity (PF=1).
0F 8A cwJPE rel16DN.S.ValidJump near if parity even (PF=1). Not supported in 64-bit mode.
0F 8A cdJPE rel32DValidValidJump near if parity even (PF=1).
0F 8B cwJPO rel16DN.S.ValidJump near if parity odd (PF=0). Not supported in 64-bit mode.
0F 8B cdJPO rel32DValidValidJump near if parity odd (PF=0).
0F 88 cwJS rel16DN.S.ValidJump near if sign (SF=1). Not supported in 64-bit mode.
OpcodeInstructionOp/
En
64-Bit
Mode
Compat/
Leg Mode
Description
------------------------------------------------------------------------------------------------------------------------------
0F 88 cdJS rel32DValidValidJump near if sign (SF=1).
0F 84 cwJZ rel16DN.S.ValidJump near if 0 (ZF=1). Not supported in 64-bit mode.
0F 84 cdJZ rel32DValidValidJump near if 0 (ZF=1).

Instruction Operand Encoding

Op/EnOperand 1Operand 2Operand 3Operand 4
DOffsetNANANA

Description

Checks the state of one or more of the status flags in the EFLAGS register (CF, OF, PF, SF, and ZF) and, if the flags are in the specified state (condition), performs a jump to the target instruction specified by the destination operand. A condition code (cc) is associated with each instruction to indicate the condition being tested for. If the condition is not satisfied, the jump is not performed and execution continues with the instruction following the Jcc instruction.

The target instruction is specified with a relative offset (a signed offset relative to the current value of the instruc-tion pointer in the EIP register). A relative offset (rel8, rel16, or rel32) is generally specified as a label in assembly code, but at the machine code level, it is encoded as a signed, 8-bit or 32-bit immediate value, which is added to the instruction pointer. Instruction coding is most efficient for offsets of -128 to +127. If the operand-size attribute is 16, the upper two bytes of the EIP register are cleared, resulting in a maximum instruction pointer size of 16 bits.

The conditions for each Jcc mnemonic are given in the "Description" column of the table on the preceding page. The terms "less" and "greater" are used for comparisons of signed integers and the terms "above" and "below" are used for unsigned integers.

Because a particular state of the status flags can sometimes be interpreted in two ways, two mnemonics are defined for some opcodes. For example, the JA (jump if above) instruction and the JNBE (jump if not below or equal) instruction are alternate mnemonics for the opcode 77H.

The Jcc instruction does not support far jumps (jumps to other code segments). When the target for the conditional jump is in a different segment, use the opposite condition from the condition being tested for the Jcc instruction, and then access the target with an unconditional far jump (JMP instruction) to the other segment. For example, the following conditional far jump is illegal:

JZ FARLABEL;

To accomplish this far jump, use the following two instructions:

JNZ BEYOND;

JMP FARLABEL;

BEYOND:

The JRCXZ, JECXZ and JCXZ instructions differ from other Jcc instructions because they do not check status flags. Instead, they check RCX, ECX or CX for 0. The register checked is determined by the address-size attribute. These instructions are useful when used at the beginning of a loop that terminates with a conditional loop instruction (such as LOOPNE). They can be used to prevent an instruction sequence from entering a loop when RCX, ECX or CX is 0. This would cause the loop to execute 264 , 232 or 64K times (not zero times).

All conditional jumps are converted to code fetches of one or two cache lines, regardless of jump address or cache-ability.

In 64-bit mode, operand size is fixed at 64 bits. JMP Short is RIP = RIP + 8-bit offset sign extended to 64 bits. JMP Near is RIP = RIP + 32-bit offset sign extended to 64-bits.

Operation

IF condition
    THEN
  tempEIP <- EIP + SignExtend(DEST);
  IF OperandSize = 16
                THEN tempEIP <- tempEIP AND 0000FFFFH;
  FI;
    IF tempEIP is not within code segment limit
          THEN #GP(0);
  ELSE EIP <- tempEIP
  FI;
FI;

Flags Affected

None

Protected Mode Exceptions

#GP(0)

  • If the offset being jumped to is beyond the limits of the CS segment.

#UD

  • If the LOCK prefix is used.

Real-Address Mode Exceptions

#GP

  • If the offset being jumped to is beyond the limits of the CS segment or is outside of the effec-tive address space from 0 to FFFFH. This condition can occur if a 32-bit address size override prefix is used.

#UD

  • If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

Same exceptions as in real address mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#GP(0)

  • If the memory address is in a non-canonical form.

#UD

  • If the LOCK prefix is used.

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