모두의 코드
MOV (Intel x86/64 assembly instruction)

작성일 : 2020-09-01 이 글은 52 번 읽혔습니다.

MOV

Move

참고 사항

아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.

OpcodeInstructionOp/
En
64-Bit
Mode
Compat/
Leg Mode
Description
88 /rMOV r/m8 r8MRValidValidMove r8 to r/m8.
REX + 88 /rMOV r/m8*** r8***MRValidN.E.Move r8 to r/m8.
89 /rMOV r/m16 r16MRValidValidMove r16 to r/m16.
89 /rMOV r/m32 r32MRValidValidMove r32 to r/m32.
REX.W + 89 /rMOV r/m64 r64MRValidN.E.Move r64 to r/m64.
8A /rMOV r8 r/m8RMValidValidMove r/m8 to r8.
REX + 8A /rMOV r8*** r/m8***RMValidN.E.Move r/m8 to r8.
8B /rMOV r16 r/m16RMValidValidMove r/m16 to r16.
8B /rMOV r32 r/m32RMValidValidMove r/m32 to r32.
REX.W + 8B /rMOV r64 r/m64RMValidN.E.Move r/m64 to r64.
8C /rMOV r/m16 Sreg**MRValidValidMove segment register to r/m16.
REX.W + 8C /rMOV r/m64 Sreg**MRValidValidMove zero extended 16-bit segment register to r/m64.
8E /rMOV Sreg r/m16**RMValidValidMove r/m16 to segment register.
REX.W + 8E /rMOV Sreg r/m64**RMValidValidMove lower 16 bits of r/m64 to segment register.
A0MOV AL moffs8*FDValidValidMove byte at (seg:offset) to AL.
REX.W + A0MOV AL moffs8*FDValidN.E.Move byte at (offset) to AL.
A1MOV AX moffs16*FDValidValidMove word at (seg:offset) to AX.
A1MOV EAX moffs32*FDValidValidMove doubleword at (seg:offset) to EAX.
REX.W + A1MOV RAX moffs64*FDValidN.E.Move quadword at (offset) to RAX.
A2MOV moffs8 ALTDValidValidMove AL to (seg:offset).
REX.W + A2MOV moffs8*** ALTDValidN.E.Move AL to (offset).
A3MOV moffs16* AXTDValidValidMove AX to (seg:offset).
A3MOV moffs32* EAXTDValidValidMove EAX to (seg:offset).
REX.W + A3MOV moffs64* RAXTDValidN.E.Move RAX to (offset).
B0+ rb ibMOV r8 imm8OIValidValidMove imm8 to r8.
REX + B0+ rb ibMOV r8*** imm8OIValidN.E.Move imm8 to r8.
B8+ rw iwMOV r16 imm16OIValidValidMove imm16 to r16.
B8+ rd idMOV r32 imm32OIValidValidMove imm32 to r32.
REX.W + B8+ rd ioMOV r64 imm64OIValidN.E.Move imm64 to r64.
C6 /0 ibMOV r/m8 imm8MIValidValidMove imm8 to r/m8.
REX + C6 /0 ibMOV r/m8*** imm8MIValidN.E.Move imm8 to r/m8.
C7 /0 iwMOV r/m16 imm16MIValidValidMove imm16 to r/m16.
C7 /0 idMOV r/m32 imm32MIValidValidMove imm32 to r/m32.
REX.W + C7 /0 idMOV r/m64 imm32MIValidN.E.Move imm32 sign extended to 64-bits to r/m64.

* The moffs8, moffs16, moffs32 and moffs64 operands specify a simple offset relative to the segment base, where 8, 16, 32 and 64 refer to the size of the data. The address-size attribute of the instruction determines the size of the offset, either 16, 32 or 64 bits.
**In 32-bit mode, the assembler may insert the 16-bit operand-size prefix with this instruction (see the following "Description" sec-tion for further information).
***In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.

Instruction Operand Encoding

Op/EnOperand 1Operand 2Operand 3Operand 4
MRModRM:r/m (w)ModRM:reg (r)NANA
RMModRM:reg (w)ModRM:r/m (r)NANA
FDAL/AX/EAX/RAXMoffsNANA
TDMoffs (w)AL/AX/EAX/RAXNANA
OIopcode + rd (w)imm8/16/32/64NANA
MIModRM:r/m (w)imm8/16/32/64NANA

Description

Copies the second operand (source operand) to the first operand (destination operand). The source operand can be an immediate value, general-purpose register, segment register, or memory location; the destination register can be a general-purpose register, segment register, or memory location. Both operands must be the same size, which can be a byte, a word, a doubleword, or a quadword.

The MOV instruction cannot be used to load the CS register. Attempting to do so results in an invalid opcode excep-tion (#UD). To load the CS register, use the far JMP, CALL, or RET instruction.

If the destination operand is a segment register (DS, ES, FS, GS, or SS), the source operand must be a valid segment selector. In protected mode, moving a segment selector into a segment register automatically causes the segment descriptor information associated with that segment selector to be loaded into the hidden (shadow) part of the segment register. While loading this information, the segment selector and segment descriptor information is validated (see the "Operation" algorithm below). The segment descriptor data is obtained from the GDT or LDT entry for the specified segment selector.

A NULL segment selector (values 0000-0003) can be loaded into the DS, ES, FS, and GS registers without causing a protection exception. However, any subsequent attempt to reference a segment whose corresponding segment register is loaded with a NULL value causes a general protection exception (#GP) and no memory reference occurs.

Loading the SS register with a MOV instruction inhibits all interrupts until after the execution of the next instruc-tion. This operation allows a stack pointer to be loaded into the ESP register with the next instruction (MOV ESP, stack-pointer value) before an interrupt occurs1 . Be aware that the LSS instruction offers a more efficient method of loading the SS and ESP registers.

When executing MOV Reg, Sreg, the processor copies the content of Sreg to the 16 least significant bits of the general-purpose register. The upper bits of the destination register are zero for most IA-32 processors (Pentium

Pro processors and later) and all Intel 64 processors, with the exception that bits 31:16 are undefined for Intel Quark X1000 processors, Pentium and earlier processors.

In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.

Operation

DEST <- SRC;
Loading a segment register while in protected mode results in special checks and actions, as described in the following listing. These checks are performed on the segment selector and the segment descriptor to which it points.
IF SS is loaded
    THEN
          IF segment selector is NULL
                THEN #GP(0); FI;
          IF segment selector index is outside descriptor table limits 
          or segment selector's RPL != CPL
          or segment is not a writable data segmentor DPL != CPL
                THEN #GP(selector); FI;
          IF segment not marked present 
                THEN #SS(selector); 
                ELSE
                      SS <- segment selector;
                      SS <- segment descriptor; FI;
FI;
IF DS, ES, FS, or GS is loaded with non-NULL selector
THEN
    IF segment selector index is outside descriptor table limits
    or segment is not a data or readable code segment
    or ((segment is a data or nonconforming code segment)
    or ((RPL > DPL) and (CPL > DPL))
          THEN #GP(selector); FI;
    IF segment not marked present
          THEN #NP(selector);
          ELSE
                SegmentRegister <- segment selector;
                SegmentRegister <- segment descriptor; FI;
FI;
IF DS, ES, FS, or GS is loaded with NULL selector
    THEN
          SegmentRegister <- segment selector;
          SegmentRegister <- segment descriptor;
FI;

Flags Affected

None

Protected Mode Exceptions

#GP(0)

  • If attempt is made to load SS register with NULL segment selector.

  • If the destination operand is in a non-writable segment.

  • If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

  • If the DS, ES, FS, or GS register contains a NULL segment selector.

#GP(selector)

  • If segment selector index is outside descriptor table limits.

  • If the SS register is being loaded and the segment selector's RPL and the segment descriptor's DPL are not equal to the CPL.

  • If the SS register is being loaded and the segment pointed to is a non-writable data segment.

  • If the DS, ES, FS, or GS register is being loaded and the segment pointed to is not a data or readable code segment.

  • If the DS, ES, FS, or GS register is being loaded and the segment pointed to is a data or nonconforming code segment, but both the RPL and the CPL are greater than the DPL.

#SS(0)

  • If a memory operand effective address is outside the SS segment limit.

#SS(selector)

  • If the SS register is being loaded and the segment pointed to is marked not present.

#NP

  • If the DS, ES, FS, or GS register is being loaded and the segment pointed to is marked not present.

#PF(fault-code)

  • If a page fault occurs.

#AC(0)

  • If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.

#UD

  • If attempt is made to load the CS register.

  • If the LOCK prefix is used.

Real-Address Mode Exceptions

#GP

  • If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS

  • If a memory operand effective address is outside the SS segment limit.

#UD

  • If attempt is made to load the CS register.

  • If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

#GP(0)

  • If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS(0)

  • If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

  • If a page fault occurs.

#AC(0)

  • If alignment checking is enabled and an unaligned memory reference is made.

#UD

  • If attempt is made to load the CS register.

  • If the LOCK prefix is used.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#GP(0)

  • If the memory address is in a non-canonical form.

  • If an attempt is made to load SS register with NULL segment selector when CPL = 3.

  • If an attempt is made to load SS register with NULL segment selector when CPL < 3 and CPL != RPL.

#GP(selector)

  • If segment selector index is outside descriptor table limits.

  • If the memory access to the descriptor table is non-canonical.

  • If the SS register is being loaded and the segment selector's RPL and the segment descriptor's DPL are not equal to the CPL.

  • If the SS register is being loaded and the segment pointed to is a nonwritable data segment.

  • If the DS, ES, FS, or GS register is being loaded and the segment pointed to is not a data or readable code segment.

  • If the DS, ES, FS, or GS register is being loaded and the segment pointed to is a data or nonconforming code segment, but both the RPL and the CPL are greater than the DPL.

#SS(0)

  • If the stack address is in a non-canonical form.

#SS(selector)

  • If the SS register is being loaded and the segment pointed to is marked not present.

#PF(fault-code)

  • If a page fault occurs.

#AC(0)

  • If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.

#UD

  • If attempt is made to load the CS register.

  • If the LOCK prefix is used.

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