모두의 코드
MOVHLPS (Intel x86/64 assembly instruction)
MOVHLPS
Move Packed Single-Precision Floating-Point Values High to Low
참고 사항
아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.
Opcode/ | Op / | 64/32 | CPUID | Description |
---|---|---|---|---|
| RM | V/V | SSE | Move two packed single-precision floating-point values from high quadword of xmm2 to low quadword of xmm1. |
| RVM | V/V | AVX | Merge two packed single-precision floating-point values from high quadword of xmm3 and low quadword of xmm2. |
| RVM | V/V | AVX512F | Merge two packed single-precision floating-point values from high quadword of xmm3 and low quadword of xmm2. |
Instruction Operand Encoding\footnote{1}
Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
---|---|---|---|---|
RM | ModRM:reg (w) | ModRM:r/m (r) | NA | NA |
RVM | ModRM:reg (w) | vvvv (r) | ModRM:r/m (r) | NA |
Description
This instruction cannot be used for memory to register moves.
128-bit two-argument form:
Moves two packed single-precision floating-point values from the high quadword of the second XMM argument (second operand) to the low quadword of the first XMM register (first argument). The quadword at bits 127:64 of the destination operand is left unchanged. Bits (MAXVL-1:128) of the corresponding destination register remain unchanged.
128-bit and EVEX three-argument form
Moves two packed single-precision floating-point values from the high quadword of the third XMM argument (third operand) to the low quadword of the destination (first operand). Copies the high quadword from the second XMM argument (second operand) to the high quadword of the destination (first operand). Bits (MAXVL-1:128) of the corresponding destination register are zeroed.
If VMOVHLPS is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or EVEX.L'L= 1 will cause an #UD exception.
Operation
MOVHLPS (128-bit two-argument form)
DEST[63:0] <- SRC[127:64] DEST[MAX_VL-1:64] (Unmodified)
VMOVHLPS (128-bit three-argument form - VEX & EVEX)
DEST[63:0] <- SRC2[127:64] DEST[127:64] <- SRC1[127:64] DEST[MAX_VL-1:128] <- 0
Intel C/C++ Compiler Intrinsic Equivalent
MOVHLPS __m128 _mm_movehl_ps(__m128 a, __m128 b)
SIMD Floating-Point Exceptions
None
Non-EVEX-encoded instruction, see Exceptions Type 7; additionally
#UD If VEX.L = 1.
EVEX-encoded instruction, see Exceptions Type E7NM.128.
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