PCMPGTQ (Intel x86/64 assembly instruction)

모두의 코드
PCMPGTQ (Intel x86/64 assembly instruction)

작성일 : 2020-09-01 이 글은 506 번 읽혔습니다.

PCMPGTQ

Compare Packed Data for Greater Than

참고 사항

아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.

Opcode/ Instruction	Op/ En	64/32 bit Mode Support	CPUID Feature Flag	Description
`66 0F 38 37 /r` PCMPGTQ xmm1 xmm2/m128	RM	V/V	SSE4_2	Compare packed signed qwords in xmm2/m128 and xmm1 for greater than.
`VEX.NDS.128.66.0F38.WIG 37 /r` VPCMPGTQ xmm1 xmm2 xmm3/m128	RVM	V/V	AVX	Compare packed signed qwords in xmm2 and xmm3/m128 for greater than.
`VEX.NDS.256.66.0F38.WIG 37 /r` VPCMPGTQ ymm1 ymm2 ymm3/m256	RVM	V/V	AVX2	Compare packed signed qwords in ymm2 and ymm3/m256 for greater than.
`EVEX.NDS.128.66.0F38.W1 37 /r` VPCMPGTQ k1 {k2} xmm2 xmm3/m128/m64bcst	FV	V/V	AVX512VL AVX512F	Compare Greater between int64 vector xmm2 and int64 vector xmm3/m128/m64bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.
`EVEX.NDS.256.66.0F38.W1 37 /r` VPCMPGTQ k1 {k2} ymm2 ymm3/m256/m64bcst	FV	V/V	AVX512VL AVX512F	Compare Greater between int64 vector ymm2 and int64 vector ymm3/m256/m64bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.
`EVEX.NDS.512.66.0F38.W1 37 /r` VPCMPGTQ k1 {k2} zmm2 zmm3/m512/m64bcst	FV	V/V	AVX512F	Compare Greater between int64 vector zmm2 and int64 vector zmm3/m512/m64bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.

Instruction Operand Encoding

Op/En	Operand 1	Operand 2	Operand 3	Operand 4
RM	ModRM:reg (r, w)	ModRM:r/m (r)	NA	NA
RVM	ModRM:reg (w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
FV	ModRM:reg (w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

Description

Performs an SIMD signed compare for the packed quadwords in the destination operand (first operand) and the source operand (second operand). If the data element in the first (destination) operand is greater than the corresponding element in the second (source) operand, the corresponding data element in the destination is set to all 1s; otherwise, it is set to 0s.

128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The first source operand and destination operand are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.

VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The first source operand and destination operand are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register.

EVEX encoded VPCMPGTD/Q: The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand (first operand) is a mask register updated according to the writemask k2.

Operation

COMPARE_QWORDS_GREATER (SRC1, SRC2)

    IF SRC1[63:0] > SRC2[63:0]
    THEN DEST[63:0] <- FFFFFFFFFFFFFFFFH;
    ELSE DEST[63:0] <- 0; FI;
    IF SRC1[127:64] > SRC2[127:64]
    THEN DEST[127:64] <- FFFFFFFFFFFFFFFFH;
    ELSE DEST[127:64] <- 0; FI;

VPCMPGTQ (VEX.128 encoded version)

DEST[127:0] <- COMPARE_QWORDS_GREATER(SRC1,SRC2)
DEST[VLMAX-1:128] <-  0

VPCMPGTQ (VEX.256 encoded version)

DEST[127:0] <- COMPARE_QWORDS_GREATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] <- COMPARE_QWORDS_GREATER(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] <-  0

VPCMPGTQ (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <-  0 TO KL-1
    i <-  j * 64
    IF k2[j] OR *no writemask*
          THEN 
                /* signed comparison */
                IF (EVEX.b = 1) AND (SRC2 *is memory*)
                      THEN CMP <-  SRC1[i+63:i] > SRC2[63:0];
                      ELSE CMP <-  SRC1[i+63:i] > SRC2[i+63:i];
                FI;
                IF CMP = TRUE
                      THEN DEST[j] <-  1;
                      ELSE DEST[j] <-  0; FI;
          ELSE  DEST[j] <-  0 ; zeroing-masking only
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <-  0

Intel C/C++ Compiler Intrinsic Equivalent

VPCMPGTQ __mmask8 _mm512_cmpgt_epi64_mask(__m512i a, __m512i b);
VPCMPGTQ __mmask8 _mm512_mask_cmpgt_epi64_mask(__mmask8 k, __m512i a,
                                               __m512i b);
VPCMPGTQ __mmask8 _mm256_cmpgt_epi64_mask(__m256i a, __m256i b);
VPCMPGTQ __mmask8 _mm256_mask_cmpgt_epi64_mask(__mmask8 k, __m256i a,
                                               __m256i b);
VPCMPGTQ __mmask8 _mm_cmpgt_epi64_mask(__m128i a, __m128i b);
VPCMPGTQ __mmask8 _mm_mask_cmpgt_epi64_mask(__mmask8 k, __m128i a, __m128i b);
(V) PCMPGTQ : __m128i _mm_cmpgt_epi64(__m128i a, __m128i b) VPCMPGTQ
    : __m256i _mm256_cmpgt_epi64(__m256i a, __m256i b);

Flags Affected

None.

SIMD Floating-Point Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Exceptions Type 4.

EVEX-encoded VPCMPGTQ, see Exceptions Type E4.

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모두의 코드 PCMPGTQ (Intel x86/64 assembly instruction)