모두의 코드
VRANGEPD (Intel x86/64 assembly instruction)

작성일 : 2020-09-01 이 글은 487 번 읽혔습니다.

VRANGEPD

Range Restriction Calculation For Packed Pairs of Float64 Values

참고 사항

아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.

Opcode/
Instruction

Op /
En

64/32
bit Mode
Support

CPUID
Feature
Flag

Description

EVEX.NDS.128.66.0F3A.W1 50 /r ib
VRANGEPD xmm1 {k1}{z} xmm2 xmm3/m128/m64bcst imm8

FV

V/V

AVX512VL
AVX512DQ

Calculate two RANGE operation output value from 2 pairs of double-precision floating-point values in xmm2 and xmm3/m128/m32bcst, store the results to xmm1 under the writemask k1. Imm8 specifies the comparison and sign of the range operation.

EVEX.NDS.256.66.0F3A.W1 50 /r ib
VRANGEPD ymm1 {k1}{z} ymm2 ymm3/m256/m64bcst imm8

FV

V/V

AVX512VL
AVX512DQ

Calculate four RANGE operation output value from 4pairs of double-precision floating-point values in ymm2 and ymm3/m256/m32bcst, store the results to ymm1 under the writemask k1. Imm8 specifies the comparison and sign of the range operation.

EVEX.NDS.512.66.0F3A.W1 50 /r ib
VRANGEPD zmm1 {k1}{z} zmm2 zmm3/m512/m64bcst{sae} imm8

FV

V/V

AVX512DQ

Calculate eight RANGE operation output value from 8 pairs of double-precision floating-point values in zmm2 and zmm3/m512/m32bcst, store the results to zmm1 under the writemask k1. Imm8 specifies the comparison and sign of the range operation.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

FV

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

Imm8

Description

This instruction calculates 2/4/8 range operation outputs from two sets of packed input double-precision FP values in the first source operand (the second operand) and the second source operand (the third operand). The range outputs are written to the destination operand (the first operand) under the writemask k1.

Bits7:4 of imm8 byte must be zero. The range operation output is performed in two parts, each configured by a two-bit control field within imm8[3:0]:

  • Imm8[1:0] specifies the initial comparison operation to be one of max, min, max absolute value or min absolute value of the input value pair. Each comparison of two input values produces an intermediate result that combines with the sign selection control (Imm8[3:2]) to determine the final range operation output.

  • Imm8[3:2] specifies the sign of the range operation output to be one of the following: from the first input value, from the comparison result, set or clear.

The encodings of Imm8[1:0] and Imm8[3:2] are shown in Figure 5-27.

o g i s S : b 1 = 2 3 [ I 8 m i u l v s b a M t c S : 1 1 = ] 0 1 8 m m I e l a v s b t c e : 0 1 = ] 0 : 1 [ 8 m l a x a 8 M t e l e S : b 0 = ] 0 : 8 m m I l a v n i l : e b 0 = ] 0 1 8 m I 0 o t n i s t e : b ] 2 : [ 8 m m ) t u s R _ e r p m C n g s t c e : 1 0 ] : [ 8 m m ) ( l r n g ) 1 C R S g i s c l e S : m 0 0 = 2 : [ m I o r e e s c e S n o i a r e O p o u 5 6 4 C 2 0 1 e : l n a [ t o e b ] [ i : [ g Z v o i ( 8 1 l p = b l 3 e o e I 1 t S 3 M b m = l e e l b t m e e u a M C e B e a t m 1 x - t S e : S i M e m 3 n 0 t t e m 3 1 A c S 2 I n c 0 S I A u S t m ] ( C n r 1 u 7 -
Figure 5-27. Imm8 Controls for VRANGEPD/SD/PS/SS

When one or more of the input value is a NAN, the comparison operation may signal invalid exception (IE). Details with one of more input value is NAN is listed in Table 5-12. If the comparison raises an IE, the sign select control (Imm8[3:2] has no effect to the range operation output, this is indicated also in Table 5-12.

When both input values are zeros of opposite signs, the comparison operation of MIN/MAX in the range compare operation is slightly different from the conceptually similar FP MIN/MAX operation that are found in the instructions VMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS for magni-tude-0, opposite-signed input cases are listed in Table 5-13.

Additionally, non-zero, equal-magnitude with opposite-sign input values perform MIN_ABS or MAX_ABS compar-ison operation with result listed in Table 5-14.

Table 5-12. Signaling of Comparison Operation of One or More NaN Input Values and Effect of Imm8[3:2]

Src1

Src2

Result

IE Signaling Due to Comparison

Imm8[3:2] Effect to Range Output

sNaN1

sNaN2

Quiet(sNaN1)

Yes

Ignored

sNaN1

qNaN2

Quiet(sNaN1)

Yes

Ignored

sNaN1

Norm2

Quiet(sNaN1)

Yes

Ignored

qNaN1

sNaN2

Quiet(sNaN2)

Yes

Ignored

qNaN1

qNaN2

qNaN1

No

Applicable

qNaN1

Norm2

Norm2

No

Applicable

Norm1

sNaN2

Quiet(sNaN2)

Yes

Ignored

Norm1

qNaN2

Norm1

No

Applicable

Table 5-13. Comparison Result for Opposite-Signed Zero Cases for MIN, MIN_ABS and MAX, MAX_ABS

MIN and MIN_AB

S

MAX and MAX_A

BS

Src1

Src2

Result

Src1

Src2

Result

+0

-0

-0

+0

-0

+0

-0

+0

-0

-0

+0

+0

Table 5-14. Comparison Result of Equal-Magnitude Input Cases for MIN_ABS and MAX_ABS, (|a| = |b|, a>0, b<0)

M

IN_ABS (|a| = |b|, a>

0, b<0)

M

AX_ABS (|a| = |b|, a>

0, b<0)

-----------

-----

----------

-

---

-

------

-----------

Src1

Src2

Result

Src1

Src2

Result

a

b

b

a

b

a

b

a

b

b

a

a

Operation

VRANGEPD (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <-  0 TO KL-1
    i <-  j * 64
    IF k1[j] OR *no writemask* THEN
                IF (EVEX.b == 1) AND (SRC2 *is memory*)
                      THEN DEST[i+63:i] <-  RangeDP (SRC1[i+63:i], SRC2[63:0], CmpOpCtl[1:0], SignSelCtl[1:0]);
                      ELSE DEST[i+63:i] <-  RangeDP (SRC1[i+63:i], SRC2[i+63:i], DAZ, CmpOpCtl[1:0], SignSelCtl[1:0]);
                FI;
    ELSE 
          IF *merging-masking* ; merging-masking
                THEN *DEST[i+63:i] remains unchanged*
                ELSE  ; zeroing-masking
                      DEST[i+63:i] = 0
          FI;
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <-  0
The following example describes a common usage of this instruction for checking that the input operand isbounded between $$\pm$$1023.
VRANGEPD zmm_dst, zmm_src, zmm_1023, 02h;
Where:
            zmm_dst is the destination operand.
            zmm_src is the input operand to compare against $$\pm$$1023 (this is SRC1).
            zmm_1023 is the reference operand, contains the value of 1023 (and this is SRC2).
            IMM=02(imm8[1:0]='10) selects the Min Absolute value operation with selection of SRC1.sign.
In case |zmm_src| < 1023 (i.e. SRC1 is smaller than 1023 in magnitude), then its value will be written intozmm_dst. Otherwise, the value stored in zmm_dst will get the value of 1023 (received on zmm_1023, which isSRC2).
However, the sign control (imm8[3:2]='00) instructs to select the sign of SRC1 received from zmm_src. So, evenin the case of |zmm_src| *   1023, the selected sign of SRC1 is kept. 
Thus, if zmm_src < -1023, the result of VRANGEPD will be the minimal value of -1023 while if zmm_src > +1023,the result of VRANGE will be the maximal value of +1023.

Intel C/C++ Compiler Intrinsic Equivalent

VRANGEPD __m512d _mm512_range_pd(__m512d a, __m512d b, int imm);
VRANGEPD __m512d _mm512_range_round_pd(__m512d a, __m512d b, int imm, int sae);
VRANGEPD __m512d _mm512_mask_range_pd(__m512 ds, __mmask8 k, __m512d a,
                                      __m512d b, int imm);
VRANGEPD __m512d _mm512_mask_range_round_pd(__m512d s, __mmask8 k, __m512d a,
                                            __m512d b, int imm, int sae);
VRANGEPD __m512d _mm512_maskz_range_pd(__mmask8 k, __m512d a, __m512d b,
                                       int imm);
VRANGEPD __m512d _mm512_maskz_range_round_pd(__mmask8 k, __m512d a, __m512d b,
                                             int imm, int sae);
VRANGEPD __m256d _mm256_range_pd(__m256d a, __m256d b, int imm);
VRANGEPD __m256d _mm256_mask_range_pd(__m256d s, __mmask8 k, __m256d a,
                                      __m256d b, int imm);
VRANGEPD __m256d _mm256_maskz_range_pd(__mmask8 k, __m256d a, __m256d b,
                                       int imm);
VRANGEPD __m128d _mm_range_pd(__m128 a, __m128d b, int imm);
VRANGEPD __m128d _mm_mask_range_pd(__m128 s, __mmask8 k, __m128d a, __m128d b,
                                   int imm);
VRANGEPD __m128d _mm_maskz_range_pd(__mmask8 k, __m128d a, __m128d b, int imm);

SIMD Floating-Point Exceptions

Invalid, Denormal

Other Exceptions

See Exceptions Type E2.

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