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HADDPD (Intel x86/64 assembly instruction)

작성일 : 2020-09-01 이 글은 933 번 읽혔습니다.

HADDPD

Packed Double-FP Horizontal Add

참고 사항

아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.

Opcode/
Instruction

Op/
En

64/32-bit
Mode

CPUID
Feature
Flag

Description

66 0F 7C /r
HADDPD xmm1 xmm2/m128

RM

V/V

SSE3

Horizontal add packed double-precision floating-point values from xmm2/m128 to xmm1.

VEX.NDS.128.66.0F.WIG 7C /r
VHADDPD xmm1 xmm2 xmm3/m128

RVM

V/V

AVX

Horizontal add packed double-precision floating-point values from xmm2 and xmm3/mem.

VEX.NDS.256.66.0F.WIG 7C /r
VHADDPD ymm1 ymm2 ymm3/m256

RVM

V/V

AVX

Horizontal add packed double-precision floating-point values from ymm2 and ymm3/mem.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (r, w)

ModRM:r/m (r)

NA

NA

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

NA

Description

Adds the double-precision floating-point values in the high and low quadwords of the destination operand and stores the result in the low quadword of the destination operand.

Adds the double-precision floating-point values in the high and low quadwords of the source operand and stores the result in the high quadword of the destination operand.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

See Figure 3-16 for HADDPD; see Figure 3-17 for VHADDPD.

6 7 2 1 [ x + 0 3 [ 1 m m x : 1 [ 8 2 m m + 0 : [ 8 m x 1 m x : u s e 7 2 1 [ : 3 6 ] : 3 [ ] 4 2 1 [ ] 6 : 7 1 [ ] 0 : 3 [ 2 1 m m 1 m m 8 2 1 2 3 m , 1 m m x D D A H 3 5 9 1 O [ 2 6 x 7 7 x ] l / m m m m 6 D m R 6 1 / m 2 4 0 m : 2 ] 6 : ] 8 x 2 6 x 6 ] 4 : M 0 t 4 6 P : ] 2 2 m 1 4 m / ] 9 / 1
Figure 3-16. HADDPD--Packed Double-FP Horizontal Add

2 R Y 3 Y X 1 1 X S 1 0 Y + 0 Y 3 X 2 3 Y 2 1 0 C + X 2 X R 0 Y 3 + E T Y 1 S X S X D + Y 2 X C
Figure 3-17. VHADDPD operation

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.

VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register.

Operation

HADDPD (128-bit Legacy SSE version)

DEST[63:0] <-  SRC1[127:64] + SRC1[63:0]
DEST[127:64] <-  SRC2[127:64] + SRC2[63:0]
DEST[VLMAX-1:128] (Unmodified)

VHADDPD (VEX.128 encoded version)

DEST[63:0] <-  SRC1[127:64] + SRC1[63:0]
DEST[127:64] <-  SRC2[127:64] + SRC2[63:0]
DEST[VLMAX-1:128] <-  0

VHADDPD (VEX.256 encoded version)

DEST[63:0] <-  SRC1[127:64] + SRC1[63:0]
DEST[127:64] <-  SRC2[127:64] + SRC2[63:0]
DEST[191:128] <-  SRC1[255:192] + SRC1[191:128]
DEST[255:192] <-  SRC2[255:192] + SRC2[191:128]

Intel C/C++ Compiler Intrinsic Equivalent

VHADDPD : __m256d _mm256_hadd_pd(__m256d a, __m256d b);
HADDPD : __m128d _mm_hadd_pd(__m128d a, __m128d b);

Exceptions

When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.

Numeric Exceptions

Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions

See Exceptions Type 2.

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