INSERTPS

Insert Scalar Single-Precision Floating-Point Value

참고 사항

Instruction Operand Encoding

Description

(register source form)

Select a single-precision floating-point element from second source as indicated by CountS bits of the immediate operand and destination operand it into the first source at the location indicated by the CountD bits of the imme-diate operand. Store in the destination and zero out destination elements based on the ZMask bits of the immediate operand.

(memory source form)

Load a floating-point element from a 32-bit memory location and destination operand it into the first source at the location indicated by the CountD bits of the immediate operand. Store in the destination and zero out destination elements based on the ZMask bits of the immediate operand.

128-bit Legacy SSE version: The first source register is an XMM register. The second source operand is either an XMM register or a 32-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding register destination are unmodified.

VEX.128 and EVEX encoded version: The destination and first source register is an XMM register. The second source operand is either an XMM register or a 32-bit memory location. The upper bits (MAXVL-1:128) of the corre-sponding register destination are zeroed.

If VINSERTPS is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an #UD exception.

Operation

VINSERTPS (VEX.128 and EVEX encoded version)

IF (SRC = REG) THEN COUNT_S <-  imm8[7:6]
    ELSE COUNT_S <-  0
COUNT_D <-  imm8[5:4]
ZMASK <-  imm8[3:0]
CASE (COUNT_S) OF
    0: TMP <-  SRC2[31:0]
    1: TMP <-  SRC2[63:32]
    2: TMP <-  SRC2[95:64]
    3: TMP <-  SRC2[127:96]
ESAC;
CASE (COUNT_D) OF
    0: TMP2[31:0] <-  TMP
          TMP2[127:32] <-  SRC1[127:32]
    1: TMP2[63:32] <-  TMP
          TMP2[31:0] <-  SRC1[31:0]
          TMP2[127:64] <-  SRC1[127:64]
    2: TMP2[95:64] <-  TMP
          TMP2[63:0] <-  SRC1[63:0]
          TMP2[127:96] <-  SRC1[127:96]
    3: TMP2[127:96] <-  TMP
          TMP2[95:0] <-  SRC1[95:0]
ESAC;
IF (ZMASK[0] = 1) THEN DEST[31:0] <-  00000000H
    ELSE DEST[31:0] <-  TMP2[31:0]
IF (ZMASK[1] = 1) THEN DEST[63:32] <-  00000000H
    ELSE DEST[63:32] <-  TMP2[63:32]
IF (ZMASK[2] = 1) THEN DEST[95:64] <-  00000000H
    ELSE DEST[95:64] <-  TMP2[95:64]
IF (ZMASK[3] = 1) THEN DEST[127:96] <-  00000000H
    ELSE DEST[127:96] <-  TMP2[127:96]
DEST[MAX_VL-1:128] <-  0

INSERTPS (128-bit Legacy SSE version)

IF (SRC = REG) THEN COUNT_S <- imm8[7:6]
    ELSE COUNT_S <- 0
COUNT_D <- imm8[5:4]
ZMASK <- imm8[3:0]
CASE (COUNT_S) OF
    0: TMP <- SRC[31:0]
    1: TMP <- SRC[63:32]
    2: TMP <- SRC[95:64]
    3: TMP <- SRC[127:96]
ESAC;
CASE (COUNT_D) OF
    0: TMP2[31:0] <- TMP
          TMP2[127:32] <- DEST[127:32]
    1: TMP2[63:32] <- TMP
          TMP2[31:0] <- DEST[31:0]
          TMP2[127:64] <- DEST[127:64]
    2: TMP2[95:64] <- TMP
TMP2[63:0] <- DEST[63:0]
          TMP2[127:96] <- DEST[127:96]
    3: TMP2[127:96] <- TMP
          TMP2[95:0] <- DEST[95:0]
ESAC;
IF (ZMASK[0] = 1) THEN DEST[31:0] <- 00000000H
    ELSE DEST[31:0] <- TMP2[31:0]
IF (ZMASK[1] = 1) THEN DEST[63:32] <- 00000000H
    ELSE DEST[63:32] <- TMP2[63:32]
IF (ZMASK[2] = 1) THEN DEST[95:64] <- 00000000H
    ELSE DEST[95:64] <- TMP2[95:64]
IF (ZMASK[3] = 1) THEN DEST[127:96] <- 00000000H
    ELSE DEST[127:96] <- TMP2[127:96]
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VINSERTPS __m128 _mm_insert_ps(__m128 dst, __m128 src, const int nidx);
INSETRTPS __m128 _mm_insert_ps(__m128 dst, __m128 src, const int nidx);

SIMD Floating-Point Exceptions

None

Other Exceptions

Non-EVEX-encoded instruction, see Exceptions Type 5; additionally

#UD If VEX.L = 0.

EVEX-encoded instruction, see Exceptions Type E9NF.

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