MOV

Move

참고 사항

Instruction Operand Encoding

Description

Copies the second operand (source operand) to the first operand (destination operand). The source operand can be an immediate value, general-purpose register, segment register, or memory location; the destination register can be a general-purpose register, segment register, or memory location. Both operands must be the same size, which can be a byte, a word, a doubleword, or a quadword.

The MOV instruction cannot be used to load the CS register. Attempting to do so results in an invalid opcode excep-tion (#UD). To load the CS register, use the far JMP, CALL, or RET instruction.

If the destination operand is a segment register (DS, ES, FS, GS, or SS), the source operand must be a valid segment selector. In protected mode, moving a segment selector into a segment register automatically causes the segment descriptor information associated with that segment selector to be loaded into the hidden (shadow) part of the segment register. While loading this information, the segment selector and segment descriptor information is validated (see the "Operation" algorithm below). The segment descriptor data is obtained from the GDT or LDT entry for the specified segment selector.

A NULL segment selector (values 0000-0003) can be loaded into the DS, ES, FS, and GS registers without causing a protection exception. However, any subsequent attempt to reference a segment whose corresponding segment register is loaded with a NULL value causes a general protection exception (#GP) and no memory reference occurs.

Loading the SS register with a MOV instruction inhibits all interrupts until after the execution of the next instruc-tion. This operation allows a stack pointer to be loaded into the ESP register with the next instruction (MOV ESP, stack-pointer value) before an interrupt occurs¹ . Be aware that the LSS instruction offers a more efficient method of loading the SS and ESP registers.

When executing MOV Reg, Sreg, the processor copies the content of Sreg to the 16 least significant bits of the general-purpose register. The upper bits of the destination register are zero for most IA-32 processors (Pentium

Pro processors and later) and all Intel 64 processors, with the exception that bits 31:16 are undefined for Intel Quark X1000 processors, Pentium and earlier processors.

In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-tional registers (R8-R15��. Use of the REX.W prefix proomtes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.

Operation

DEST 0 SRC;
Loading a segment register while in protected mode results in special checks and actions, as described in the following listing. These checks are performed on the segment selector and the segment descriptor to which it points.
IF SS is loaded
    THEN
          IF segment selector is NULL
                THEN #GP(0); FI;
          IF segment selector index is outside descriptor table limits 
          or segment selector's RPL 0 CPL
          or segment is not a writable data segmentor DPL 0 CPL
                THEN #GP(selector); FI;
          IF segment not marked present 
                THEN #SS�s� elector); 
                ELSE
                      SS 0 segment selector;
                      SS 0 segment descriptor; FI;
FI;
IF DS, ES, FS, or GS is loaded with non-NULL selector
THEN
    IF segment selector index is outside descriptor table limits
    or segment is not a data or readable code segment
    or ((segment is a data or nonconforming code segment)
    or ((RPL > DPL) and (CPL > DPL))
          THEN #GP(selector); FI;
    IF segment not marked present
          THEN #NP(selector);
          ELSE
                SegmentRegister 0 segment selector;
                SegmentRegister 0 segment descriptor; FI;
FI;
IF DS, ES, FS, or GS is loaded with NULL selector
    THEN
          SegmentRegister 0 segment selector;
          SegmentRegister 0 segment descriptor;
FI;

Flags Affected

None

Protected Mode Exceptions

#GP(0)

• If attempt is made to load SS register with NULL segment selector.

• If the destination operand is in a non-writable segment.

• If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

• If the DS, ES, FS, or GS register contains a NULL segment selector.

#GP(selectorp�

• If segment selector index is outside descriptor table limits.

• If the SS register is being loaded and the segment selector's RPL and the segment descriptorp�s DPL are not equal to the CPL.

• If the SS register is being loaded and the segment pointed to is a non-writable data segment.

• If the DS, ES, FS, or GS register is being loaded and the segment pointed to is not a data or readable code segment.

• If the DS, ES, FS, or GS register is being loaded and the segment pointed to is a data or nonconforming code segment, but both the RPL and the CPL are greater than the DPL.

#SS(0)

• If a memory operand effective address is outside the SS segment limit.

#SS(selector)

• If the SS register is being loaded and the segment pointed to is marked not present.

#NP

• If the DS, ES, FS, or GS register is being loaded and the segment pointed to is marked not present.

#PF(fault-code)

• If a page fault occurs.

#AC(0p�

• If alignment checking is enabled and a unnaligned memory reference is made while the current privilege level is 3.

#UD

• If attempt is made to load the CS register.

• If the LOCK prefix is used.

Real-Address Mode Exceptions

#GP

• If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS

• If a memory operand effective address is outside the SS segment limit.

#UD

• If attempt is made to load the CS register.

• If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

#GP(0)

• If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS(0)

• If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

• If a page fault occurs.

#AC(0p�

• If alignment checking is enabled and an unaligned memory reference is made.

#UD

• If attempt is made to load the CS register.

• If the LOCK prefix is used.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#GP(0)

• If the memory address is in a non-canonical form.

• If an attempt is made to load SS register with NULL segment selector when CPL = 3.

• If an attempt is made to load SS register with NULL segment selector when CPL < 3 and CPL 0 RPL.

#GP(selector)

• If segment selector index is outside descriptor table limits.

• If the memory access to the descriptor table is non-canonical.

• If the SS register is being loaded and the segment selector's RPL and the segment descriptorP�s DPL are not equal to the CPL.

• If the SS register is being loaded and the segment pointed to is a nonwritable data segment.

• If the DS, ES, FS, or GS register is being loaded and the segment pointed to is not a data or readable code segment.

• If the DS, ES, FS, or GS register is being loaded and the segment pointed to is a data or nonconforming code segment, but both the RPL and the CPL are greater than the DPL.

#SS(0)

• If the stack address is in a non-canonical form.

#SS(selector)

• If the SS register is being loaded and the segment pointed to is marked not present.

#PF(fault-code)

• If a page fault occurs.

#AC(0P�

• If alignment checking is enabled and a unnaligned memory reference is made while the current privilege level is 3.

#UD

• If attempt is made to load the CS register.

• If the LOCK prefix is used.

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