VFPCLASSPD (Intel x86/64 assembly instruction)

모두의 코드
VFPCLASSPD (Intel x86/64 assembly instruction)

작성일 : 2020-09-01 이 글은 563 번 읽혔습니다.

VFPCLASSPD

Tests Types Of a Packed Float64 Values

참고 사항

아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.

Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
`EVEX.128.66.0F3A.W1 66 /r ib` VFPCLASSPD k2 {k1} xmm2/m128/m64bcst imm8	FV	V/V	AVX512VL AVX512DQ	Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.
`EVEX.256.66.0F3A.W1 66 /r ib` VFPCLASSPD k2 {k1} ymm2/m256/m64bcst imm8	FV	V/V	AVX512VL AVX512DQ	Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.
`EVEX.512.66.0F3A.W1 66 /r ib` VFPCLASSPD k2 {k1} zmm2/m512/m64bcst imm8	FV	V/V	AVX512DQ	Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.

Instruction Operand Encoding

Op/En	Operand 1	Operand 2	Operand 3	Operand 4
FV	ModRM:reg (w)	ModRM:r/m (r)	NA	NA

Description

The FPCLASSPD instruction checks the packed double precision floating point values for special categories, speci-fied by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input data element is classified against. The classified results of all specified categories of an input value are ORed together to form the final boolean result for the input element. The result of each element is written to the corre-sponding bit in a mask register k2 according to the writemask k1. Bits [MAXKL-1:8/4/2] of the destination are cleared.

The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category is listed in Table 5-6.

Figure 5-13. Imm8 Byte Specifier of Special Case FP Values for VFPCLASSPD/SD/PS/SS

Table 5-6. Classifier Operations for VFPCLASSPD/SD/PS/SS

The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Bits	Imm8[0]	Imm8[1]	Imm8[2]	Imm8[3]	Imm8[4]	Imm8[5]	Imm8[6]	Imm8[7]
Category	QNAN	PosZero	NegZero	PosINF	NegINF	Denormal	Negative	SNAN
Classifier	Checks for QNaN	Checks for +0	Checks for -0	Checks for +INF	Checks for -INF	Checks for Denormal	Checks for Negative finite	Checks for SNaN

Operation

VFPCLASSPD (EVEX Encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <-  0 TO KL-1
    i <-  j * 64
    IF k1[j] OR *no writemask*
          THEN 
                IF (EVEX.b == 1) AND (SRC *is memory*)
                      THEN
                            DEST[j] <-  CheckFPClassDP(SRC1[63:0], imm8[7:0]);
                      ELSE 
                            DEST[j] <-  CheckFPClassDP(SRC1[i+63:i], imm8[7:0]);
                FI;
          ELSE DEST[j] <-  0 ; zeroing-masking only
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <-  0

Intel C/C++ Compiler Intrinsic Equivalent

VFPCLASSPD __mmask8 _mm512_fpclass_pd_mask(__m512d a, int c);
VFPCLASSPD __mmask8 _mm512_mask_fpclass_pd_mask(__mmask8 m, __m512d a,
                                                int c) VFPCLASSPD __mmask8
    _mm256_fpclass_pd_mask(__m256d a, int c) VFPCLASSPD __mmask8
    _mm256_mask_fpclass_pd_mask(__mmask8 m, __m256d a,
                                int c) VFPCLASSPD __mmask8
    _mm_fpclass_pd_mask(__m128d a, int c) VFPCLASSPD __mmask8
    _mm_mask_fpclass_pd_mask(__mmask8 m, __m128d a, int c)

SIMD Floating-Point Exceptions

None

Other Exceptions

See Exceptions Type E4

#UD If EVEX.vvvv != 1111B.

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모두의 코드 VFPCLASSPD (Intel x86/64 assembly instruction)