VSHUFF32x4, VSHUFF64x2, VSHUFI32x4, VSHUFI64x2s (Intel x86/64 assembly instruction)

모두의 코드
VSHUFF32x4, VSHUFF64x2, VSHUFI32x4, VSHUFI64x2s (Intel x86/64 assembly instruction)

작성일 : 2020-09-01 이 글은 571 번 읽혔습니다.

VSHUFF32x4, VSHUFF64x2, VSHUFI32x4, VSHUFI64x2

Shuffle Packed Values at 128-bit Granularity

참고 사항

아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.

Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
`EVEX.NDS.256.66.0F3A.W0 23 /r ibVSHUFF32X4 ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst, imm8`	FV	V/V	AVX512VL AVX512F	Shuffle 128-bit packed single-precision floating-point values selected by imm8 from ymm2 and ymm3/m256/m32bcst and place results in ymm1 subject to writemask k1.
`EVEX.NDS.512.66.0F3A.W0 23 /r ib` VSHUFF32x4 zmm1{k1}{z} zmm2 zmm3/m512/m32bcst imm8	FV	V/V	AVX512F	Shuffle 128-bit packed single-precision floating-point values selected by imm8 from zmm2 and zmm3/m512/m32bcst and place results in zmm1 subject to writemask k1.
`EVEX.NDS.256.66.0F3A.W1 23 /r ibVSHUFF64X2 ymm1{k1}{z}, ymm2, ymm3/m256/m64bcst, imm8`	FV	V/V	AVX512VL AVX512F	Shuffle 128-bit packed double-precision floating-point values selected by imm8 from ymm2 and ymm3/m256/m64bcst and place results in ymm1 subject to writemask k1.
`EVEX.NDS.512.66.0F3A.W1 23 /r ib` VSHUFF64x2 zmm1{k1}{z} zmm2 zmm3/m512/m64bcst imm8	FV	V/V	AVX512F	Shuffle 128-bit packed double-precision floating-point values selected by imm8 from zmm2 and zmm3/m512/m64bcst and place results in zmm1 subject to writemask k1.
`EVEX.NDS.256.66.0F3A.W0 43 /r ibVSHUFI32X4 ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst, imm8`	FV	V/V	AVX512VL AVX512F	Shuffle 128-bit packed double-word values selected by imm8 from ymm2 and ymm3/m256/m32bcst and place results in ymm1 subject to writemask k1.
`EVEX.NDS.512.66.0F3A.W0 43 /r ib` VSHUFI32x4 zmm1{k1}{z} zmm2 zmm3/m512/m32bcst imm8	FV	V/V	AVX512F	Shuffle 128-bit packed double-word values selected by imm8 from zmm2 and zmm3/m512/m32bcst and place results in zmm1 subject to writemask k1.
`EVEX.NDS.256.66.0F3A.W1 43 /r ibVSHUFI64X2 ymm1{k1}{z}, ymm2, ymm3/m256/m64bcst, imm8`	FV	V/V	AVX512VL AVX512F	Shuffle 128-bit packed quad-word values selected by imm8 from ymm2 and ymm3/m256/m64bcst and place results in ymm1 subject to writemask k1.
`EVEX.NDS.512.66.0F3A.W1 43 /r ib` VSHUFI64x2 zmm1{k1}{z} zmm2 zmm3/m512/m64bcst imm8	FV	V/V	AVX512F	Shuffle 128-bit packed quad-word values selected by imm8 from zmm2 and zmm3/m512/m64bcst and place results in zmm1 subject to writemask k1.

Instruction Operand Encoding

Op/En	Operand 1	Operand 2	Operand 3	Operand 4
FV	ModRM:reg (w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

Description

256-bit Version: Moves one of the two 128-bit packed single-precision floating-point values from the first source operand (second operand) into the low 128-bit of the destination operand (first operand); moves one of the two packed 128-bit floating-point values from the second source operand (third operand) into the high 128-bit of the destination operand. The selector operand (third operand) determines which values are moved to the destination operand.

512-bit Version: Moves two of the four 128-bit packed single-precision floating-point values from the first source operand (second operand) into the low 256-bit of each double qword of the destination operand (first operand); moves two of the four packed 128-bit floating-point values from the second source operand (third operand) into the high 256-bit of the destination operand. The selector operand (third operand) determines which values are moved to the destination operand.

The first source operand is a vector register. The second source operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a vector register.

The writemask updates the destination operand with the granularity of 32/64-bit data elements.

Operation

VSHUFF32x4 (EVEX versions)

(KL, VL) = (8, 256), (16, 512)
FOR j <-  0 TO KL-1
    i <-  j * 32
    IF (EVEX.b = 1) AND (SRC2 *is memory*)
          THEN TMP_SRC2[i+31:i] <-  SRC2[31:0]
          ELSE TMP_SRC2[i+31:i] <-  SRC2[i+31:i]
    FI;
ENDFOR;
IF VL = 256
    TMP_DEST[127:0] <-  Select2(SRC1[255:0], imm8[0]);
    TMP_DEST[255:128] <-  Select2(SRC2[255:0], imm8[1]);
FI;
IF VL = 512
    TMP_DEST[127:0] <-  Select4(SRC1[511:0], imm8[1:0]);
    TMP_DEST[255:128] <-  Select4(SRC1[511:0], imm8[3:2]);
    TMP_DEST[383:256] <-  Select4(TMP_SRC2[511:0], imm8[5:4]);
    TMP_DEST[511:384] <-  Select4(TMP_SRC2[511:0], imm8[7:6]);
FI;
FOR j <-  0 TO KL-1
    i <-  j * 32
    IF k1[j] OR *no writemask*
          THEN DEST[i+31:i] <-  TMP_DEST[i+31:i]
          ELSE 
                IF *merging-masking* ; merging-masking
                      THEN *DEST[i+31:i] remains unchanged*
                      ELSE *zeroing-masking* ; zeroing-masking
                            THEN DEST[i+31:i] <-  0
                FI;
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <-  0

VSHUFF64x2 (EVEX 512-bit version)

(KL, VL) = (4, 256), (8, 512)
FOR j <-  0 TO KL-1
    i <-  j * 64
    IF (EVEX.b = 1) AND (SRC2 *is memory*)
          THEN TMP_SRC2[i+63:i] <-  SRC2[63:0]
          ELSE TMP_SRC2[i+63:i] <-  SRC2[i+63:i]
    FI;
ENDFOR;
IF VL = 256
    TMP_DEST[127:0] <-  Select2(SRC1[255:0], imm8[0]);
    TMP_DEST[255:128] <-  Select2(SRC2[255:0], imm8[1]);
FI;
IF VL = 512
    TMP_DEST[127:0] <-  Select4(SRC1[511:0], imm8[1:0]);
    TMP_DEST[255:128] <-  Select4(SRC1[511:0], imm8[3:2]);
    TMP_DEST[383:256] <-  Select4(TMP_SRC2[511:0], imm8[5:4]);
    TMP_DEST[511:384] <-  Select4(TMP_SRC2[511:0], imm8[7:6]);
FI;
FOR j <-  0 TO KL-1
    i <-  j * 64
    IF k1[j] OR *no writemask*
          THEN DEST[i+63:i] <-  TMP_DEST[i+63:i]
          ELSE 
                IF *merging-masking* ; merging-masking
                      THEN *DEST[i+63:i] remains unchanged*
                      ELSE *zeroing-masking* ; zeroing-masking
                            THEN DEST[i+63:i] <-!= 0
                FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <-  0

VSHUFI32x4 (EVEX 512-bit version)

(KL, VL) = (8, 256), (16, 512)
FOR j <-  0 TO KL-1
    i <-  j * 32
    IF (EVEX.b = 1) AND (SRC2 *is memory*)
          THEN TMP_SRC2[i+31:i] <-  SRC2[31:0]
          ELSE TMP_SRC2[i+31:i] <-  SRC2[i+31:i]
    FI;
ENDFOR;
IF VL = 256
    TMP_DEST[127:0] <-  Select2(SRC1[255:0], imm8[0]);
    TMP_DEST[255:128] <-  Select2(SRC2[255:0], imm8[1]);
FI;
IF VL = 512
    TMP_DEST[127:0] <-  Select4(SRC1[511:0], imm8[1:0]);
    TMP_DEST[255:128] <-  Select4(SRC1[511:0], imm8[3:2]);
    TMP_DEST[383:256] <-  Select4(TMP_SRC2[511:0], imm8[5:4]);
    TMP_DEST[511:384] <-  Select4(TMP_SRC2[511:0], imm8[7:6]);
FI;
FOR j <-  0 TO KL-1
    i <-  j * 32
IF k1[j] OR *no writemask*
          THEN DEST[i+31:i] <-  TMP_DEST[i+31:i]
          ELSE 
                IF *merging-masking* ; merging-masking
                      THEN *DEST[i+31:i] remains unchanged*
                      ELSE *zeroing-masking* ; zeroing-masking
                            THEN DEST[i+31:i] <-  0
                FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <-  0

VSHUFI64x2 (EVEX 512-bit version)

(KL, VL) = (4, 256), (8, 512)
FOR j <-  0 TO KL-1
    i <-  j * 64
    IF (EVEX.b = 1) AND (SRC2 *is memory*)
          THEN TMP_SRC2[i+63:i] <-  SRC2[63:0]
          ELSE TMP_SRC2[i+63:i] <-  SRC2[i+63:i]
    FI;
ENDFOR;
IF VL = 256
    TMP_DEST[127:0] <-  Select2(SRC1[255:0], imm8[0]);
    TMP_DEST[255:128] <-  Select2(SRC2[255:0], imm8[1]);
FI;
IF VL = 512
    TMP_DEST[127:0] <-  Select4(SRC1[511:0], imm8[1:0]);
    TMP_DEST[255:128] <-  Select4(SRC1[511:0], imm8[3:2]);
    TMP_DEST[383:256] <-  Select4(TMP_SRC2[511:0], imm8[5:4]);
    TMP_DEST[511:384] <-  Select4(TMP_SRC2[511:0], imm8[7:6]);
FI;
FOR j <-  0 TO KL-1
    i <-  j * 64
    IF k1[j] OR *no writemask*
          THEN DEST[i+63:i] <-  TMP_DEST[i+63:i]
          ELSE 
                IF *merging-masking* ; merging-masking
                      THEN *DEST[i+63:i] remains unchanged*
                      ELSE *zeroing-masking* ; zeroing-masking
                            THEN DEST[i+63:i] <-!= 0
                FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <-  0

Intel C/C++ Compiler Intrinsic Equivalent

VSHUFI32x4 __m512i _mm512_shuffle_i32x4(__m512i a, __m512i b, int imm);
VSHUFI32x4 __m512i _mm512_mask_shuffle_i32x4(__m512i s, __mmask16 k, __m512i a,
                                             __m512i b, int imm);
VSHUFI32x4 __m512i _mm512_maskz_shuffle_i32x4(__mmask16 k, __m512i a, __m512i b,
                                              int imm);
VSHUFI32x4 __m256i _mm256_shuffle_i32x4(__m256i a, __m256i b, int imm);
VSHUFI32x4 __m256i _mm256_mask_shuffle_i32x4(__m256i s, __mmask8 k, __m256i a,
                                             __m256i b, int imm);
VSHUFI32x4 __m256i _mm256_maskz_shuffle_i32x4(__mmask8 k, __m256i a, __m256i b,
                                              int imm);
VSHUFF32x4 __m512 _mm512_shuffle_f32x4(__m512 a, __m512 b, int imm);
VSHUFF32x4 __m512 _mm512_mask_shuffle_f32x4(__m512 s, __mmask16 k, __m512 a,
                                            __m512 b, int imm);
VSHUFF32x4 __m512 _mm512_maskz_shuffle_f32x4(__mmask16 k, __m512 a, __m512 b,
                                             int imm);
VSHUFI64x2 __m512i _mm512_shuffle_i64x2(__m512i a, __m512i b, int imm);
VSHUFI64x2 __m512i _mm512_mask_shuffle_i64x2(__m512i s, __mmask8 k, __m512i b,
                                             __m512i b, int imm);
VSHUFI64x2 __m512i _mm512_maskz_shuffle_i64x2(__mmask8 k, __m512i a, __m512i b,
                                              int imm);
VSHUFF64x2 __m512d _mm512_shuffle_f64x2(__m512d a, __m512d b, int imm);
VSHUFF64x2 __m512d _mm512_mask_shuffle_f64x2(__m512d s, __mmask8 k, __m512d a,
                                             __m512d b, int imm);
VSHUFF64x2 __m512d _mm512_maskz_shuffle_f64x2(__mmask8 k, __m512d a, __m512d b,
                                              int imm);

SIMD Floating-Point Exceptions

None

Other Exceptions

See Exceptions Type E4NF.

#UD If EVEX.L'L = 0 for VSHUFF32x4/VSHUFF64x2.

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모두의 코드 VSHUFF32x4, VSHUFF64x2, VSHUFI32x4, VSHUFI64x2s (Intel x86/64 assembly instruction)