모두의 코드
AESKEYGENASSIST (Intel x86/64 assembly instruction)

작성일 : 2020-09-01 이 글은 1068 번 읽혔습니다.

AESKEYGENASSIST

AES Round Key Generation Assist

참고 사항

아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.

Opcode/
Instruction

Op/
En

64/32-bit
Mode

CPUID
Feature
Flag

Description

66 0F 3A DF /r ib
AESKEYGENASSIST xmm1 xmm2/m128 imm8

RMI

V/V

AES

Assist in AES round key generation using an 8 bits Round Constant (RCON) specified in the immediate byte, operating on 128 bits of data specified in xmm2/m128 and stores the result in xmm1.

VEX.128.66.0F3A.WIG DF /r ib
VAESKEYGENASSIST xmm1 xmm2/m128 imm8

RMI

V/V

Both AES andAVX flags

Assist in AES round key generation using 8 bits Round Constant (RCON) specified in the immediate byte, operating on 128 bits of data specified in xmm2/m128 and stores the result in xmm1.

Instruction Operand Encoding

Op/En

Operand 1

Operand2

Operand3

Operand4

RMI

ModRM:reg (w)

ModRM:r/m (r)

imm8

NA

Description

Assist in expanding the AES cipher key, by computing steps towards generating a round key for encryption, using 128-bit data specified in the source operand and an 8-bit round constant specified as an immediate, store the result in the destination operand.

The destination operand is an XMM register. The source operand can be an XMM register or a 128-bit memory loca-tion.

128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.

VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.

Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

AESKEYGENASSIST

X3[31:0] <- SRC [127: 96];
X2[31:0] <- SRC [95: 64];
X1[31:0] <- SRC [63: 32];
X0[31:0] <- SRC [31: 0];
RCON[31:0] <- ZeroExtend(Imm8[7:0]);
DEST[31:0] <- SubWord(X1);
DEST[63:32 ] <- RotWord( SubWord(X1) ) XOR RCON;
DEST[95:64] <- SubWord(X3);
DEST[127:96] <- RotWord( SubWord(X3) ) XOR RCON;
DEST[VLMAX-1:128] (Unmodified)

VAESKEYGENASSIST

X3[31:0] <-  SRC [127: 96];
X2[31:0] <-  SRC [95: 64];
X1[31:0] <-  SRC [63: 32];
X0[31:0] <-  SRC [31: 0];
RCON[31:0] <-  ZeroExtend(Imm8[7:0]);
DEST[31:0] <-  SubWord(X1);
DEST[63:32 ] <-  RotWord( SubWord(X1) ) XOR RCON;
DEST[95:64] <-  SubWord(X3);
DEST[127:96] <-  RotWord( SubWord(X3) ) XOR RCON;
DEST[VLMAX-1:128] <-  0;

Intel C/C++ Compiler Intrinsic Equivalent

(V) AESKEYGENASSIST : __m128i _mm_aeskeygenassist(__m128i, const int)

SIMD Floating-Point Exceptions

None

Other Exceptions

See Exceptions Type 4; additionally

#UD If VEX.vvvv -> 1111B.

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