모두의 코드
CVTPS2PD (Intel x86/64 assembly instruction)
CVTPS2PD
Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
참고 사항
아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.
Opcode/ | Op / | 64/32 | CPUID | Description |
---|---|---|---|---|
| RM | V/V | SSE2 | Convert two packed single-precision floating-point values in xmm2/m64 to two packed double-precision floating-point values in xmm1. |
| RM | V/V | AVX | Convert two packed single-precision floating-point values in xmm2/m64 to two packed double-precision floating-point values in xmm1. |
| RM | V/V | AVX | Convert four packed single-precision floating-point values in xmm2/m128 to four packed double-precision floating-point values in ymm1. |
| HV | V/V | AVX512VL | Convert two packed single-precision floating-point values in xmm2/m64/m32bcst to packed double-precision floating-point values in xmm1 with writemask k1. |
| HV | V/V | AVX512VL | Convert four packed single-precision floating-point values in xmm2/m128/m32bcst to packed double-precision floating-point values in ymm1 with writemask k1. |
| HV | V/V | AVX512F | Convert eight packed single-precision floating-point values in ymm2/m256/b32bcst to eight packed double-precision floating-point values in zmm1 with writemask k1. |
Instruction Operand Encoding
Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
---|---|---|---|---|
RM | ModRM:reg (w) | ModRM:r/m (r) | NA | NA |
HV | ModRM:reg (w) | ModRM:r/m (r) | NA | NA |
Description
Converts two, four or eight packed single-precision floating-point values in the source operand (second operand) to two, four or eight packed double-precision floating-point values in the destination operand (first operand).
EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64-bits) register, a 256/128/64-bit memory location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.
VEX.256 encoded version: The source operand is an XMM register or 128- bit memory location. The destination operand is a YMM register. Bits (MAXVL-1:256) of the corresponding destination ZMM register are zeroed.
VEX.128 encoded version: The source operand is an XMM register or 64- bit memory location. The destination operand is a XMM register. The upper Bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 64- bit memory location. The destination operand is an XMM register. The upper Bits (MAXVL-1:128) of the corresponding ZMM register destination are unmodified.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTPS2PD (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512) FOR j <- 0 TO KL-1 i <- j * 64 k <- j * 32 IF k1[j] OR *no writemask* THEN DEST[i+63:i] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[k+31:k]) ELSE IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged* ELSE ; zeroing-masking DEST[i+63:i] <- 0 FI FI; ENDFOR DEST[MAX_VL-1:VL] <- 0
VCVTPS2PD (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512) FOR j <- 0 TO KL-1 i <- j * 64 k <- j * 32 IF k1[j] OR *no writemask* THEN IF (EVEX.b = 1) THEN DEST[i+63:i] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0]) ELSE DEST[i+63:i] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[k+31:k]) FI; ELSE IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged* ELSE ; zeroing-masking DEST[i+63:i] <- 0 FI FI; ENDFOR DEST[MAX_VL-1:VL] <- 0
VCVTPS2PD (VEX.256 encoded version)
DEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0]) DEST[127:64] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32]) DEST[191:128] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[95:64]) DEST[255:192] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[127:96) DEST[MAX_VL-1:256] <- 0
VCVTPS2PD (VEX.128 encoded version)
DEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0]) DEST[127:64] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32]) DEST[MAX_VL-1:128] <- 0
CVTPS2PD (128-bit Legacy SSE version)
DEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0]) DEST[127:64] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32]) DEST[MAX_VL-1:128] (unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2PD __m512d _mm512_cvtps_pd(__m256 a); VCVTPS2PD __m512d _mm512_mask_cvtps_pd(__m512d s, __mmask8 k, __m256 a); VCVTPS2PD __m512d _mm512_maskz_cvtps_pd(__mmask8 k, __m256 a); VCVTPS2PD __m512d _mm512_cvt_roundps_pd(__m256 a, int sae); VCVTPS2PD __m512d _mm512_mask_cvt_roundps_pd(__m512d s, __mmask8 k, __m256 a, int sae); VCVTPS2PD __m512d _mm512_maskz_cvt_roundps_pd(__mmask8 k, __m256 a, int sae); VCVTPS2PD __m256d _mm256_mask_cvtps_pd(__m256d s, __mmask8 k, __m128 a); VCVTPS2PD __m256d _mm256_maskz_cvtps_pd(__mmask8 k, __m128a); VCVTPS2PD __m128d _mm_mask_cvtps_pd(__m128d s, __mmask8 k, __m128 a); VCVTPS2PD __m128d _mm_maskz_cvtps_pd(__mmask8 k, __m128 a); VCVTPS2PD __m256d _mm256_cvtps_pd(__m128 a) CVTPS2PD __m128d _mm_cvtps_pd(__m128 a)
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3;
EVEX-encoded instructions, see Exceptions Type E3.
#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
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