모두의 코드
PMINUD, PMINUQs (Intel x86/64 assembly instruction)
PMINUD, PMINUQ
Minimum of Packed Unsigned Integers
참고 사항
아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.
Opcode/ | Op/ | 64/32 | CPUID | Description |
---|---|---|---|---|
| RM | V/V | SSE4_1 | Compare packed unsigned dword integers in xmm1 and xmm2/m128 and store packed minimum values in xmm1. |
| RVM | V/V | AVX | Compare packed unsigned dword integers in xmm2 and xmm3/m128 and store packed minimum values in xmm1. |
| RVM | V/V | AVX2 | Compare packed unsigned dword integers in ymm2 and ymm3/m256 and store packed minimum values in ymm1. |
| FV | V/V | AVX512VL | Compare packed unsigned dword integers in xmm2 and xmm3/m128/m32bcst and store packed minimum values in xmm1 under writemask k1. |
| FV | V/V | AVX512VL | Compare packed unsigned dword integers in ymm2 and ymm3/m256/m32bcst and store packed minimum values in ymm1 under writemask k1. |
| FV | V/V | AVX512F | Compare packed unsigned dword integers in zmm2 and zmm3/m512/m32bcst and store packed minimum values in zmm1 under writemask k1. |
| FV | V/V | AVX512VL | Compare packed unsigned qword integers in xmm2 and xmm3/m128/m64bcst and store packed minimum values in xmm1 under writemask k1. |
| FV | V/V | AVX512VL | Compare packed unsigned qword integers in ymm2 and ymm3/m256/m64bcst and store packed minimum values in ymm1 under writemask k1. |
| FV | V/V | AVX512F | Compare packed unsigned qword integers in zmm2 and zmm3/m512/m64bcst and store packed minimum values in zmm1 under writemask k1. |
Instruction Operand Encoding
Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
---|---|---|---|---|
RM | ModRM:reg (r, w) | ModRM:r/m (r) | NA | NA |
RVM | ModRM:reg (w) | VEX.vvvv (r) | ModRM:r/m (r) | NA |
FV | ModRM:reg (w) | EVEX.vvvv (r) | ModRM:r/m (r) | NA |
Description
Performs a SIMD compare of the packed unsigned dword/qword integers in the second source operand and the first source operand and returns the minimum value for each pair of integers to the destination operand.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding destination register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding destination register are zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The first source and destination operands are YMM registers. Bits (MAXVL-1:256) of the corresponding destination register are zeroed.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.
Operation
PMINUD (128-bit Legacy SSE version)
PMINUD instruction for 128-bit operands: IF DEST[31:0] < SRC[31:0] THEN DEST[31:0] <- DEST[31:0]; ELSE DEST[31:0] <- SRC[31:0]; FI; (* Repeat operation for 2nd through 7th words in source and destination operands *) IF DEST[127:96] < SRC[127:96] THEN DEST[127:96] <- DEST[127:96]; ELSE DEST[127:96] <- SRC[127:96]; FI; DEST[MAX_VL-1:128] (Unmodified)
VPMINUD (VEX.128 encoded version)
VPMINUD instruction for 128-bit operands: IF SRC1[31:0] < SRC2[31:0] THEN DEST[31:0] <- SRC1[31:0]; ELSE DEST[31:0] <- SRC2[31:0]; FI; (* Repeat operation for 2nd through 3rd dwords in source and destination operands *) IF SRC1[127:96] < SRC2[127:96] THEN DEST[127:96] <- SRC1[127:96]; ELSE DEST[127:96] <- SRC2[127:96]; FI; DEST[MAX_VL-1:128] <- 0
VPMINUD (VEX.256 encoded version)
VPMINUD instruction for 128-bit operands: IF SRC1[31:0] < SRC2[31:0] THEN DEST[31:0] <- SRC1[31:0]; ELSE DEST[31:0] <- SRC2[31:0]; FI; (* Repeat operation for 2nd through 7th dwords in source and destination operands *) IF SRC1[255:224] < SRC2[255:224] THEN DEST[255:224] <- SRC1[255:224]; ELSE DEST[255:224] <- SRC2[255:224]; FI; DEST[MAX_VL-1:256] <- 0
VPMINUD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512) FOR j <- 0 TO KL-1 i <- j * 32 IF k1[j] OR *no writemask* THEN IF (EVEX.b = 1) AND (SRC2 *is memory*) THEN IF SRC1[i+31:i] < SRC2[31:0] THEN DEST[i+31:i] <- SRC1[i+31:i]; ELSE DEST[i+31:i] <- SRC2[31:0]; FI; ELSE IF SRC1[i+31:i] < SRC2[i+31:i] THEN DEST[i+31:i] <- SRC1[i+31:i]; ELSE DEST[i+31:i] <- SRC2[i+31:i]; FI; FI; ELSE IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged* ELSE ; zeroing-masking DEST[i+31:i] <- 0 FI FI; ENDFOR; DEST[MAX_VL-1:VL] <- 0
VPMINUQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512) FOR j <- 0 TO KL-1 i <- j * 64 IF k1[j] OR *no writemask* THEN IF (EVEX.b = 1) AND (SRC2 *is memory*) THEN IF SRC1[i+63:i] < SRC2[63:0] THEN DEST[i+63:i] <- SRC1[i+63:i]; ELSE DEST[i+63:i] <- SRC2[63:0]; FI; ELSE IF SRC1[i+63:i] < SRC2[i+63:i] THEN DEST[i+63:i] <- SRC1[i+63:i]; ELSE DEST[i+63:i] <- SRC2[i+63:i]; FI; FI; ELSE IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged* ELSE ; zeroing-masking DEST[i+63:i] <- 0 FI FI; ENDFOR; DEST[MAX_VL-1:VL] <- 0
Intel C/C++ Compiler Intrinsic Equivalent
VPMINUD __m512i _mm512_min_epu32(__m512i a, __m512i b); VPMINUD __m512i _mm512_mask_min_epu32(__m512i s, __mmask16 k, __m512i a, __m512i b); VPMINUD __m512i _mm512_maskz_min_epu32(__mmask16 k, __m512i a, __m512i b); VPMINUQ __m512i _mm512_min_epu64(__m512i a, __m512i b); VPMINUQ __m512i _mm512_mask_min_epu64(__m512i s, __mmask8 k, __m512i a, __m512i b); VPMINUQ __m512i _mm512_maskz_min_epu64(__mmask8 k, __m512i a, __m512i b); VPMINUD __m256i _mm256_mask_min_epu32(__m256i s, __mmask16 k, __m256i a, __m256i b); VPMINUD __m256i _mm256_maskz_min_epu32(__mmask16 k, __m256i a, __m256i b); VPMINUQ __m256i _mm256_mask_min_epu64(__m256i s, __mmask8 k, __m256i a, __m256i b); VPMINUQ __m256i _mm256_maskz_min_epu64(__mmask8 k, __m256i a, __m256i b); VPMINUD __m128i _mm_mask_min_epu32(__m128i s, __mmask8 k, __m128i a, __m128i b); VPMINUD __m128i _mm_maskz_min_epu32(__mmask8 k, __m128i a, __m128i b); VPMINUQ __m128i _mm_mask_min_epu64(__m128i s, __mmask8 k, __m128i a, __m128i b); VPMINUQ __m128i _mm_maskz_min_epu64(__mmask8 k, __m128i a, __m128i b); (V) PMINUD __m128i _mm_min_epu32(__m128i a, __m128i b); VPMINUD __m256i _mm256_min_epu32(__m256i a, __m256i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
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