모두의 코드
VFNMADD132PS, VFNMADD213PS, VFNMADD231PSs (Intel x86/64 assembly instruction)
VFNMADD132PS, VFNMADD213PS, VFNMADD231PS
Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
참고 사항
아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.
Opcode/ | Op/ | 64/32 | CPUID | Description |
---|---|---|---|---|
| RVM | V/V | FMA | Multiply packed single-precision floating-point values from xmm1 and xmm3/mem, negate the multiplication result andadd to xmm2 and put result in xmm1. |
| RVM | V/V | FMA | Multiply packed single-precision floating-point values from xmm1 and xmm2, negate the multiplication result and add to xmm3/mem and put result in xmm1. |
| RVM | V/V | FMA | Multiply packed single-precision floating-point values from xmm2 and xmm3/mem, negate the multiplication result andadd to xmm1 and put result in xmm1. |
| RVM | V/V | FMA | Multiply packed single-precision floating-point values from ymm1 and ymm3/mem, negate the multiplication result andadd to ymm2 and put result in ymm1. |
| RVM | V/V | FMA | Multiply packed single-precision floating-point values from ymm1 and ymm2, negate the multiplication result and add to ymm3/mem and put result in ymm1. |
| RVM | V/V | FMA | Multiply packed single-precision floating-point values from ymm2 and ymm3/mem, negate the multiplication result and add to ymm1 and put result in ymm1. |
| FV | V/V | AVX512VL | Multiply packed single-precision floating-point values from xmm1 and xmm3/m128/m32bcst, negate the multiplication result and add to xmm2 and put result in xmm1. |
| FV | V/V | AVX512VL | Multiply packed single-precision floating-point values from xmm1 and xmm2, negate the multiplication result and add to xmm3/m128/m32bcst and put result in xmm1. |
| FV | V/V | AVX512VL | Multiply packed single-precision floating-point values from xmm2 and xmm3/m128/m32bcst, negate the multiplication result and add to xmm1 and put result in xmm1. |
| FV | V/V | AVX512VL | Multiply packed single-precision floating-point values from ymm1 and ymm3/m256/m32bcst, negate the multiplication result and add to ymm2 and put result in ymm1. |
| FV | V/V | AVX512VL | Multiply packed single-precision floating-point values from ymm1 and ymm2, negate the multiplication result and add to ymm3/m256/m32bcst and put result in ymm1. |
| FV | V/V | AVX512VL | Multiply packed single-precision floating-point values from ymm2 and ymm3/m256/m32bcst, negate the multiplication result and add to ymm1 and put result in ymm1. |
| FV | V/V | AVX512VL | Multiply packed single-precision floating-point values from zmm1 and zmm3/m512/m32bcst, negate the multiplication result and add to zmm2 and put result in zmm1. |
| FV | V/V | AVX512F | Multiply packed single-precision floating-point values from zmm1 and zmm2, negate the multiplication result and add to zmm3/m512/m32bcst and put result in zmm1. |
| FV | V/V | AVX512F | Multiply packed single-precision floating-point values from zmm2 and zmm3/m512/m32bcst, negate the multiplication result and add to zmm1 and put result in zmm1. |
Instruction Operand Encoding
Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
---|---|---|---|---|
RVM | ModRM:reg (r, w) | VEX.vvvv (r) | ModRM:r/m (r) | NA |
FV | ModRM:reg (r, w) | EVEX.vvvv (r) | ModRM:r/m (r) | NA |
Description
VFNMADD132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first source operand to the four, eight or sixteen packed single-precision floating-point values in the third source operand, adds the negated infinite precision intermediate result to the four, eight or sixteen packed single-preci-sion floating-point values in the second source operand, performs rounding and stores the resulting four, eight or sixteen packed single-precision floating-point values to the destination operand (first source operand).
VFNMADD213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second source operand to the four, eight or sixteen packed single-precision floating-point values in the first source operand, adds the negated infinite precision intermediate result to the four, eight or sixteen packed single-preci-sion floating-point values in the third source operand, performs rounding and stores the resulting the four, eight or sixteen packed single-precision floating-point values to the destination operand (first source operand).
VFNMADD231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second source operand to the four, eight or sixteen packed single-precision floating-point values in the third source operand, adds the negated infinite precision intermediate result to the four, eight or sixteen packed single-preci-sion floating-point values in the first source operand, performs rounding and stores the resulting four, eight or sixteen packed single-precision floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-tion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is condition-ally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in regfield. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a YMM register or a 256-bit memory location and encoded in rmfield.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in regfield. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit memory location and encoded in rmfield. The upper 128 bits of the YMM destination register are zeroed.
Operation
VFNMADD132PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN MAXNUM <- 2 ELSEIF (VEX.256) MAXNUM <- 4 FI For i = 0 to MAXNUM-1 { n <- 32*i; DEST[n+31:n] <- RoundFPControl_MXCSR(- (DEST[n+31:n]*SRC3[n+31:n]) + SRC2[n+31:n]) } IF (VEX.128) THEN DEST[MAX_VL-1:128] <- 0 ELSEIF (VEX.256) DEST[MAX_VL-1:256] <- 0 FI
VFNMADD213PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN MAXNUM <- 2 ELSEIF (VEX.256) MAXNUM <- 4 FI For i = 0 to MAXNUM-1 { n <- 32*i; DEST[n+31:n] <- RoundFPControl_MXCSR(- (SRC2[n+31:n]*DEST[n+31:n]) + SRC3[n+31:n]) } IF (VEX.128) THEN DEST[MAX_VL-1:128] <- 0 ELSEIF (VEX.256) DEST[MAX_VL-1:256] <- 0 FI
VFNMADD231PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN MAXNUM <- 2 ELSEIF (VEX.256) MAXNUM <- 4 FI For i = 0 to MAXNUM-1 { n <- 32*i; DEST[n+31:n] <- RoundFPControl_MXCSR(- (SRC2[n+31:n]*SRC3[n+31:n]) + DEST[n+31:n]) } IF (VEX.128) THEN DEST[MAX_VL-1:128] <- 0 ELSEIF (VEX.256) DEST[MAX_VL-1:256] <- 0 FI
VFNMADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1) THEN SET_RM(EVEX.RC); ELSE SET_RM(MXCSR.RM); FI; FOR j <- 0 TO KL-1 i <- j * 32 IF k1[j] OR *no writemask* THEN DEST[i+31:i] <- RoundFPControl(-(DEST[i+31:i]*SRC3[i+31:i]) + SRC2[i+31:i]) ELSE IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged* ELSE ; zeroing-masking DEST[i+31:i] <- 0 FI FI; ENDFOR DEST[MAX_VL-1:VL] <- 0
VFNMADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512) FOR j <- 0 TO KL-1 i <- j * 32 IF k1[j] OR *no writemask* THEN IF (EVEX.b = 1) THEN DEST[i+31:i] <- RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[31:0]) + SRC2[i+31:i]) ELSE DEST[i+31:i] <- RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[i+31:i]) + SRC2[i+31:i]) FI; ELSE IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged* ELSE ; zeroing-masking DEST[i+31:i] <- 0 FI FI; ENDFOR DEST[MAX_VL-1:VL] <- 0
VFNMADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1) THEN SET_RM(EVEX.RC); ELSE SET_RM(MXCSR.RM); FI; FOR j <- 0 TO KL-1 i <- j * 32 IF k1[j] OR *no writemask* THEN DEST[i+31:i] <- RoundFPControl(-(SRC2[i+31:i]*DEST[i+31:i]) + SRC3[i+31:i]) ELSE IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged* ELSE ; zeroing-masking DEST[i+31:i] <- 0 FI FI; ENDFOR DEST[MAX_VL-1:VL] <- 0
VFNMADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512) FOR j <- 0 TO KL-1 i <- j * 32 IF k1[j] OR *no writemask* THEN IF (EVEX.b = 1) THEN DEST[i+31:i] <- RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) + SRC3[31:0]) ELSE DEST[i+31:i] <- RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) + SRC3[i+31:i]) FI; ELSE IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged* ELSE ; zeroing-masking DEST[i+31:i] <- 0 FI FI; ENDFOR DEST[MAX_VL-1:VL] <- 0
VFNMADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1) THEN SET_RM(EVEX.RC); ELSE SET_RM(MXCSR.RM); FI; FOR j <- 0 TO KL-1 i <- j * 32 IF k1[j] OR *no writemask* THEN DEST[i+31:i] <- RoundFPControl(-(SRC2[i+31:i]*SRC3[i+31:i]) + DEST[i+31:i]) ELSE IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged* ELSE ; zeroing-masking DEST[i+31:i] <- 0 FI FI; ENDFOR DEST[MAX_VL-1:VL] <- 0
VFNMADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512) FOR j <- 0 TO KL-1 i <- j * 32 IF k1[j] OR *no writemask* THEN IF (EVEX.b = 1) THEN DEST[i+31:i] <- RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[31:0]) + DEST[i+31:i]) ELSE DEST[i+31:i] <- RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[i+31:i]) + DEST[i+31:i]) FI; ELSE IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged* ELSE ; zeroing-masking DEST[i+31:i] <- 0 FI FI; ENDFOR DEST[MAX_VL-1:VL] <- 0
Intel C/C++ Compiler Intrinsic Equivalent
VFNMADDxxxPS __m512 _mm512_fnmadd_ps(__m512 a, __m512 b, __m512 c); VFNMADDxxxPS __m512 _mm512_fnmadd_round_ps(__m512 a, __m512 b, __m512 c, int r); VFNMADDxxxPS __m512 _mm512_mask_fnmadd_ps(__m512 a, __mmask16 k, __m512 b, __m512 c); VFNMADDxxxPS __m512 _mm512_maskz_fnmadd_ps(__mmask16 k, __m512 a, __m512 b, __m512 c); VFNMADDxxxPS __m512 _mm512_mask3_fnmadd_ps(__m512 a, __m512 b, __m512 c, __mmask16 k); VFNMADDxxxPS __m512 _mm512_mask_fnmadd_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r); VFNMADDxxxPS __m512 _mm512_maskz_fnmadd_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r); VFNMADDxxxPS __m512 _mm512_mask3_fnmadd_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r); VFNMADDxxxPS __m256 _mm256_mask_fnmadd_ps(__m256 a, __mmask8 k, __m256 b, __m256 c); VFNMADDxxxPS __m256 _mm256_maskz_fnmadd_ps(__mmask8 k, __m256 a, __m256 b, __m256 c); VFNMADDxxxPS __m256 _mm256_mask3_fnmadd_ps(__m256 a, __m256 b, __m256 c, __mmask8 k); VFNMADDxxxPS __m128 _mm_mask_fnmadd_ps(__m128 a, __mmask8 k, __m128 b, __m128 c); VFNMADDxxxPS __m128 _mm_maskz_fnmadd_ps(__mmask8 k, __m128 a, __m128 b, __m128 c); VFNMADDxxxPS __m128 _mm_mask3_fnmadd_ps(__m128 a, __m128 b, __m128 c, __mmask8 k); VFNMADDxxxPS __m128 _mm_fnmadd_ps(__m128 a, __m128 b, __m128 c); VFNMADDxxxPS __m256 _mm256_fnmadd_ps(__m256 a, __m256 b, __m256 c);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
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