모두의 코드
XORPD (Intel x86/64 assembly instruction)

작성일 : 2020-09-01 이 글은 813 번 읽혔습니다.

XORPD

Bitwise Logical XOR of Packed Double Precision Floating-Point Values

참고 사항

아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.

Opcode/
Instruction

Op /
En

64/32
bit Mode
Support

CPUID
Feature
Flag

Description

66 0F 57/r
XORPD xmm1 xmm2/m128

RM

V/V

SSE2

Return the bitwise logical XOR of packed double-precision floating-point values in xmm1 and xmm2/mem.

VEX.NDS.128.66.0F.WIG 57 /r
VXORPD xmm1 xmm2 xmm3/m128

RVM

V/V

AVX

Return the bitwise logical XOR of packed double-precision floating-point values in xmm2 and xmm3/mem.

VEX.NDS.256.66.0F.WIG 57 /r
VXORPD ymm1 ymm2 ymm3/m256

RVM

V/V

AVX

Return the bitwise logical XOR of packed double-precision floating-point values in ymm2 and ymm3/mem.

EVEX.NDS.128.66.0F.W1 57 /r
VXORPD xmm1 {k1}{z} xmm2 xmm3/m128/m64bcst

FV

V/V

AVX512VL
AVX512DQ

Return the bitwise logical XOR of packed double-precision floating-point values in xmm2 and xmm3/m128/m64bcst subject to writemask k1.

EVEX.NDS.256.66.0F.W1 57 /r
VXORPD ymm1 {k1}{z} ymm2 ymm3/m256/m64bcst

FV

V/V

AVX512VL
AVX512DQ

Return the bitwise logical XOR of packed double-precision floating-point values in ymm2 and ymm3/m256/m64bcst subject to writemask k1.

EVEX.NDS.512.66.0F.W1 57 /r
VXORPD zmm1 {k1}{z} zmm2 zmm3/m512/m64bcst

FV

V/V

AVX512DQ

Return the bitwise logical XOR of packed double-precision floating-point values in zmm2 and zmm3/m512/m64bcst subject to writemask k1.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (r, w)

ModRM:r/m (r)

NA

NA

RVM

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

NA

FV

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

NA

Description

Performs a bitwise logical XOR of the two, four or eight packed double-precision floating-point values from the first source operand and the second source operand, and stores the result in the destination operand

EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand can be a ZMM register or a vector memory location. The destination operand is a ZMM register conditionally updated with writemask k1.

VEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register (conditionally updated with writemask k1 in case of EVEX). The upper bits (MAXVL-1:256) of the corresponding ZMM register destination are zeroed.

VEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register (conditionally updated with writemask k1 in case of EVEX). The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding register destination are unmodified.

Operation

VXORPD (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <-  0 TO KL-1
    i <-  j * 64
    IF k1[j] OR *no writemask* THEN
IF (EVEX.b == 1) AND (SRC2 *is memory*)
                      THEN DEST[i+63:i] <-  SRC1[i+63:i] BITWISE XOR SRC2[63:0];
                      ELSE DEST[i+63:i] <-  SRC1[i+63:i] BITWISE XOR SRC2[i+63:i];
                FI;
          ELSE 
                IF *merging-masking* ; merging-masking
                      THEN *DEST[i+63:i] remains unchanged*
                      ELSE *zeroing-masking* ; zeroing-masking
                            DEST[i+63:i] = 0
                FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <-  0

VXORPD (VEX.256 encoded version)

DEST[63:0] <-  SRC1[63:0] BITWISE XOR SRC2[63:0]
DEST[127:64] <-  SRC1[127:64] BITWISE XOR SRC2[127:64]
DEST[191:128] <-  SRC1[191:128] BITWISE XOR SRC2[191:128]
DEST[255:192] <-  SRC1[255:192] BITWISE XOR SRC2[255:192]
DEST[MAX_VL-1:256] <-  0

VXORPD (VEX.128 encoded version)

DEST[63:0] <-  SRC1[63:0] BITWISE XOR SRC2[63:0]
DEST[127:64] <-  SRC1[127:64] BITWISE XOR SRC2[127:64]
DEST[MAX_VL-1:128] <-  0

XORPD (128-bit Legacy SSE version)

DEST[63:0] <-  DEST[63:0] BITWISE XOR SRC[63:0]
DEST[127:64] <-  DEST[127:64] BITWISE XOR SRC[127:64]
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VXORPD __m512d _mm512_xor_pd(__m512d a, __m512d b);
VXORPD __m512d _mm512_mask_xor_pd(__m512d a, __mmask8 m, __m512d b);
VXORPD __m512d _mm512_maskz_xor_pd(__mmask8 m, __m512d a);
VXORPD __m256d _mm256_xor_pd(__m256d a, __m256d b);
VXORPD __m256d _mm256_mask_xor_pd(__m256d a, __mmask8 m, __m256d b);
VXORPD __m256d _mm256_maskz_xor_pd(__mmask8 m, __m256d a);
XORPD __m128d _mm_xor_pd(__m128d a, __m128d b);
VXORPD __m128d _mm_mask_xor_pd(__m128d a, __mmask8 m, __m128d b);
VXORPD __m128d _mm_maskz_xor_pd(__mmask8 m, __m128d a);

SIMD Floating-Point Exceptions

None

Other Exceptions

Non-EVEX-encoded instructions, see Exceptions Type 4.

EVEX-encoded instructions, see Exceptions Type E4.

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