모두의 코드
ADDSUBPD (Intel x86/64 assembly instruction)
ADDSUBPD
Packed Double-FP Add/Subtract
참고 사항
아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.
Opcode/ | Op/ | 64/32-bit | CPUID | Description |
---|---|---|---|---|
| RM | V/V | SSE3 | Add/subtract double-precision floating-point values from xmm2/m128 to xmm1. |
| RVM | V/V | AVX | Add/subtract packed double-precision floating-point values from xmm3/mem to xmm2 and stores result in xmm1. |
| RVM | V/V | AVX | Add / subtract packed double-precision floating-point values from ymm3/mem to ymm2 and stores result in ymm1. |
Instruction Operand Encoding
Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
---|---|---|---|---|
RM | ModRM:reg (r, w) | ModRM:r/m (r) | NA | NA |
RVM | ModRM:reg (w) | VEX.vvvv (r) | ModRM:r/m (r) | NA |
Description
Adds odd-numbered double-precision floating-point values of the first source operand (second operand) with the corresponding double-precision floating-point values from the second source operand (third operand); stores the result in the odd-numbered values of the destination operand (first operand). Subtracts the even-numbered double-precision floating-point values from the second source operand from the corresponding double-precision floating values in the first source operand; stores the result into the even-numbered values of the destination operand.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified. See Figure 3-3.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register.
Operation
ADDSUBPD (128-bit Legacy SSE version)
DEST[63:0] <- DEST[63:0] - SRC[63:0] DEST[127:64] <- DEST[127:64] + SRC[127:64] DEST[VLMAX-1:128] (Unmodified)
VADDSUBPD (VEX.128 encoded version)
DEST[63:0] <- SRC1[63:0] - SRC2[63:0] DEST[127:64] <- SRC1[127:64] + SRC2[127:64] DEST[VLMAX-1:128] <- 0
VADDSUBPD (VEX.256 encoded version)
DEST[63:0] <- SRC1[63:0] - SRC2[63:0] DEST[127:64] <- SRC1[127:64] + SRC2[127:64] DEST[191:128] <- SRC1[191:128] - SRC2[191:128] DEST[255:192] <- SRC1[255:192] + SRC2[255:192]
Intel C/C++ Compiler Intrinsic Equivalent
ADDSUBPD : __m128d _mm_addsub_pd(__m128d a, __m128d b) VADDSUBPD : __m256d _mm256_addsub_pd(__m256d a, __m256d b)
Exceptions
When the source operand is a memory operand, it must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal.
Other Exceptions
See Exceptions Type 2.
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