CVTDQ2PS

Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values

참고 사항

Instruction Operand Encoding

Description

Converts four, eight or sixteen packed signed doubleword integers in the source operand to four, eight or sixteen packed single-precision floating-point values in the destination operand.

EVEX encoded versions: The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-tion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.

VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination operand is a YMM register. Bits (MAXVL-1:256) of the corresponding register destination are zeroed.

VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding register destination are zeroed.

128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination operand is an XMM register. The upper Bits (MAXVL-1:128) of the corresponding register destination are unmod-ified.

VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

Operation

VCVTDQ2PS (EVEX encoded versions) when SRC operand is a register

(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1) 
    THEN
          SET_RM(EVEX.RC);  ; refer to Table 2-4 in the Intel(R) Architecture Instruction Set Extensions Programming Reference
    ELSE 
          SET_RM(MXCSR.RM);  ; refer to Table 2-4 in the Intel(R) Architecture Instruction Set Extensions Programming Reference
FI;
FOR j <-  0 TO KL-1
    i <-  j * 32
    IF k1[j] OR *no writemask*
          THEN DEST[i+31:i] <-
                Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])
          ELSE 
                IF *merging-masking* ; merging-masking
                      THEN *DEST[i+31:i] remains unchanged*
                      ELSE  ; zeroing-masking
                            DEST[i+31:i] <-  0
                FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <-  0

VCVTDQ2PS (EVEX encoded versions) when SRC operand is a memory source

(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <-  0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
          THEN 
                IF (EVEX.b = 1) 
                      THEN
                            DEST[i+31:i] <-
                Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
                      ELSE 
                            DEST[i+31:i] <-
                Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])
                FI;
          ELSE 
                IF *merging-masking* ; merging-masking
                      THEN *DEST[i+31:i] remains unchanged*
                      ELSE  ; zeroing-masking
                            DEST[i+31:i] <-  0
                FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <-  0

VCVTDQ2PS (VEX.256 encoded version)

DEST[31:0] <-  Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
DEST[63:32] <-  Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
DEST[95:64] <-  Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
DEST[127:96] <-  Convert_Integer_To_Single_Precision_Floating_Point(SRC[127:96)
DEST[159:128] <-  Convert_Integer_To_Single_Precision_Floating_Point(SRC[159:128])
DEST[191:160] <-  Convert_Integer_To_Single_Precision_Floating_Point(SRC[191:160])
DEST[223:192] <-  Convert_Integer_To_Single_Precision_Floating_Point(SRC[223:192])
DEST[255:224] <-  Convert_Integer_To_Single_Precision_Floating_Point(SRC[255:224)
DEST[MAX_VL-1:256] <-  0

VCVTDQ2PS (VEX.128 encoded version)

DEST[31:0] <-  Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
DEST[63:32] <-  Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
DEST[95:64] <-  Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
DEST[127:96] <-  Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)
DEST[MAX_VL-1:128] <-  0

CVTDQ2PS (128-bit Legacy SSE version)

DEST[31:0] <-  Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
DEST[63:32] <-  Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
DEST[95:64] <-  Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
DEST[127:96] <-  Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)
DEST[MAX_VL-1:128] (unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VCVTDQ2PS __m512 _mm512_cvtepi32_ps(__m512i a);
VCVTDQ2PS __m512 _mm512_mask_cvtepi32_ps(__m512 s, __mmask16 k, __m512i a);
VCVTDQ2PS __m512 _mm512_maskz_cvtepi32_ps(__mmask16 k, __m512i a);
VCVTDQ2PS __m512 _mm512_cvt_roundepi32_ps(__m512i a, int r);
VCVTDQ2PS __m512 _mm512_mask_cvt_roundepi_ps(__m512 s, __mmask16 k, __m512i a,
                                             int r);
VCVTDQ2PS __m512 _mm512_maskz_cvt_roundepi32_ps(__mmask16 k, __m512i a, int r);
VCVTDQ2PS __m256 _mm256_mask_cvtepi32_ps(__m256 s, __mmask8 k, __m256i a);
VCVTDQ2PS __m256 _mm256_maskz_cvtepi32_ps(__mmask8 k, __m256i a);
VCVTDQ2PS __m128 _mm_mask_cvtepi32_ps(__m128 s, __mmask8 k, __m128i a);
VCVTDQ2PS __m128 _mm_maskz_cvtepi32_ps(__mmask8 k, __m128i a);
CVTDQ2PS __m256 _mm256_cvtepi32_ps(__m256i src) CVTDQ2PS __m128
    _mm_cvtepi32_ps(__m128i src)

SIMD Floating-Point Exceptions

Precision

Other Exceptions

VEX-encoded instructions, see Exceptions Type 2;

EVEX-encoded instructions, see Exceptions Type E2.

#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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