Return from Procedure
Opcode*
Instruction
Op/ En
64-Bit Mode
Compat/ Leg Mode
Description
C3
RET
NP
Valid
Valid
Near return to calling procedure.
CB
RET
NP
Valid
Valid
Far return to calling procedure.
C2 iw
RET imm16
I
Valid
Valid
Near return to calling procedure and pop imm16 bytes from stack.
CA iw
RET imm16
I
Valid
Valid
Far return to calling procedure and pop imm16 bytes from stack.
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
I
imm16
NA
NA
NA
Transfers program control to a return address located on the top of the stack. The address is usually placed on the stack by a CALL instruction, and the return is made to the instruction that follows the CALL instruction.
The optional source operand specifies the number of stack bytes to be released after the return address is popped; the default is none. This operand can be used to release parameters from the stack that were passed to the called procedure and are no longer needed. It must be used when the CALL instruction used to switch to a new procedure uses a call gate with a non-zero word count to access the new procedure. Here, the source operand for the RET instruction must specify the same number of bytes as is specified in the word count field of the call gate.
The RET instruction can be used to execute three different types of returns:
Near return -- A return to a calling procedure within the current code segment (the segment currently pointed to by the CS register), sometimes referred to as an intrasegment return.
Far return -- A return to a calling procedure located in a different segment than the current code segment, sometimes referred to as an intersegment return.
Inter-privilege-level far return -- A far return to a different privilege level than that of the currently executing program or procedure.
The inter-privilege-level return type can only be executed in protected mode. See the section titled "Calling Proce-dures Using Call and RET" in Chapter 6 of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for detailed information on near, far, and inter-privilege-level returns.
When executing a near return, the processor pops the return instruction pointer (offset) from the top of the stack into the EIP register and begins program execution at the new instruction pointer. The CS register is unchanged.
When executing a far return, the processor pops the return instruction pointer from the top of the stack into the EIP register, then pops the segment selector from the top of the stack into the CS register. The processor then begins program execution in the new code segment at the new instruction pointer.
The mechanics of an inter-privilege-level far return are similar to an intersegment return, except that the processor examines the privilege levels and access rights of the code and stack segments being returned to deter-mine if the control transfer is allowed to be made. The DS, ES, FS, and GS segment registers are cleared by the RET instruction during an inter-privilege-level return if they refer to segments that are not allowed to be accessed at the new privilege level. Since a stack switch also occurs on an inter-privilege level return, the ESP and SS registers are loaded from the stack.
If parameters are passed to the called procedure during an inter-privilege level call, the optional source operand must be used with the RET instruction to release the parameters on the return. Here, the parameters are released both from the called procedure's stack and the calling procedure's stack (that is, the stack being returned to).
In 64-bit mode, the default operation size of this instruction is the stack-address size, i.e. 64 bits. This applies to near returns, not far returns; the default operation size of far returns is 32 bits.
(* Near return *)
IF instruction = near return
THEN;
IF OperandSize = 32
THEN
IF top 4 bytes of stack not within stack limits
THEN #SS(0); FI;
EIP <- Pop();
ELSE
IF OperandSize = 64
THEN
IF top 8 bytes of stack not within stack limits
THEN #SS(0); FI;
RIP <- Pop();
ELSE (* OperandSize = 16 *)
IF top 2 bytes of stack not within stack limits
THEN #SS(0); FI;
tempEIP <- Pop();
tempEIP <- tempEIP AND 0000FFFFH;
IF tempEIP not within code segment limits
THEN #GP(0); FI;
EIP <- tempEIP;
FI;
FI;
IF instruction has immediate operand
THEN (* Release parameters from stack *)
IF StackAddressSize = 32
THEN
ESP <- ESP + SRC;
ELSE
IF StackAddressSize = 64
THEN
RSP <- RSP + SRC;
ELSE (* StackAddressSize = 16 *)
SP <- SP + SRC;
FI;
FI;
FI;
FI;
(* Real-address mode or virtual-8086 mode *)
IF ((PE = 0) or (PE = 1 AND VM = 1)) and instruction = far return
THEN
IF OperandSize = 32
THEN
IF top 8 bytes of stack not within stack limits
THEN #SS(0); FI;
EIP <- Pop();
CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded *)
ELSE (* OperandSize = 16 *)
IF top 4 bytes of stack not within stack limits
THEN #SS(0); FI;
tempEIP <- Pop();
tempEIP <- tempEIP AND 0000FFFFH;
IF tempEIP not within code segment limits
THEN #GP(0); FI;
EIP <- tempEIP;
CS <- Pop(); (* 16-bit pop *)
FI;
IF instruction has immediate operand
THEN (* Release parameters from stack *)
SP <- SP + (SRC AND FFFFH);
FI;
FI;
(* Protected mode, not virtual-8086 mode *)
IF (PE = 1 and VM = 0 and IA32_EFER.LMA = 0) and instruction = far return
THEN
IF OperandSize = 32
THEN
IF second doubleword on stack is not within stack limits
THEN #SS(0); FI;
ELSE (* OperandSize = 16 *)
IF second word on stack is not within stack limits
THEN #SS(0); FI;
FI;
IF return code segment selector is NULL
THEN #GP(0); FI;
IF return code segment selector addresses descriptor beyond descriptor table limit
THEN #GP(selector); FI;
Obtain descriptor to which return code segment selector points from descriptor table;
IF return code segment descriptor is not a code segment
THEN #GP(selector); FI;
IF return code segment selector RPL < CPL
THEN #GP(selector); FI;
IF return code segment descriptor is conforming
and return code segment DPL > return code segment selector RPL
THEN #GP(selector); FI;
IF return code segment descriptor is non-conforming and return code segment DPL != return code segment selector RPL
THEN #GP(selector); FI;
IF return code segment descriptor is not present
THEN #NP(selector); FI:
IF return code segment selector RPL > CPL
THEN GOTO RETURN-TO-OUTER-PRIVILEGE-LEVEL;
ELSE GOTO RETURN-TO-SAME-PRIVILEGE-LEVEL;
FI;
FI;
RETURN-SAME-PRIVILEGE-LEVEL:
IF the return instruction pointer is not within the return code segment limit
THEN #GP(0); FI;
IF OperandSize = 32
THEN
EIP <- Pop();
CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded *)
ELSE (* OperandSize = 16 *)
EIP <- Pop();
EIP <- EIP AND 0000FFFFH;
CS <- Pop(); (* 16-bit pop *)
FI;
IF instruction has immediate operand
THEN (* Release parameters from stack *)
IF StackAddressSize = 32
THEN
ESP <- ESP + SRC;
ELSE (* StackAddressSize = 16 *)
SP <- SP + SRC;
FI;
FI;
RETURN-TO-OUTER-PRIVILEGE-LEVEL:
IF top (16 + SRC) bytes of stack are not within stack limits (OperandSize = 32)
or top (8 + SRC) bytes of stack are not within stack limits (OperandSize = 16)
THEN #SS(0); FI;
Read return segment selector;
IF stack segment selector is NULL
THEN #GP(0); FI;
IF return stack segment selector index is not within its descriptor table limits
THEN #GP(selector); FI;
Read segment descriptor pointed to by return segment selector;
IF stack segment selector RPL != RPL of the return code segment selector
or stack segment is not a writable data segment
or stack segment descriptor DPL != RPL of the return code segment selector
THEN #GP(selector); FI;
IF stack segment not present
THEN #SS(StackSegmentSelector); FI;
IF the return instruction pointer is not within the return code segment limit
THEN #GP(0); FI;
CPL <- ReturnCodeSegmentSelector(RPL);
IF OperandSize = 32
THEN
EIP <- Pop();
CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded; segment descriptor loaded *)
CS(RPL) <- CPL;
IF instruction has immediate operand
THEN (* Release parameters from called procedure's stack *)
IF StackAddressSize = 32
THEN
ESP <- ESP + SRC;
ELSE (* StackAddressSize = 16 *)
SP <- SP + SRC;
FI;
FI;
tempESP <- Pop();
tempSS <- Pop(); (* 32-bit pop, high-order 16 bits discarded; seg. descriptor loaded *)
ESP <- tempESP;
SS <- tempSS;
ELSE (* OperandSize = 16 *)
EIP <- Pop();
EIP <- EIP AND 0000FFFFH;
CS <- Pop(); (* 16-bit pop; segment descriptor loaded *)
CS(RPL) <- CPL;
IF instruction has immediate operand
THEN (* Release parameters from called procedure's stack *)
IF StackAddressSize = 32
THEN
ESP <- ESP + SRC;
ELSE (* StackAddressSize = 16 *)
SP <- SP + SRC;
FI;
FI;
tempESP <- Pop();
tempSS <- Pop(); (* 16-bit pop; segment descriptor loaded *)
ESP <- tempESP;
SS <- tempSS;
FI;
FOR each of segment register (ES, FS, GS, and DS)
DO
IF segment register points to data or non-conforming code segment
and CPL > segment descriptor DPL (* DPL in hidden part of segment register *)
THEN SegmentSelector <- 0; (* Segment selector invalid *)
FI;
OD;
IF instruction has immediate operand
THEN (* Release parameters from calling procedure's stack *)
IF StackAddressSize = 32
THEN
ESP <- ESP + SRC;
ELSE (* StackAddressSize = 16 *)
SP <- SP + SRC;
FI;
FI;
(* IA-32e Mode *)
IF (PE = 1 and VM = 0 and IA32_EFER.LMA = 1) and instruction = far return
THEN
IF OperandSize = 32
THEN
IF second doubleword on stack is not within stack limits
THEN #SS(0); FI;
IF first or second doubleword on stack is not in canonical space
THEN #SS(0); FI;
ELSE
IF OperandSize = 16
THEN
IF second word on stack is not within stack limits
THEN #SS(0); FI;
IF first or second word on stack is not in canonical space
THEN #SS(0); FI;
ELSE (* OperandSize = 64 *)
IF first or second quadword on stack is not in canonical space
THEN #SS(0); FI;
FI
FI;
IF return code segment selector is NULL
THEN GP(0); FI;
IF return code segment selector addresses descriptor beyond descriptor table limit
THEN GP(selector); FI;
IF return code segment selector addresses descriptor in non-canonical space
THEN GP(selector); FI;
Obtain descriptor to which return code segment selector points from descriptor table;
IF return code segment descriptor is not a code segment
THEN #GP(selector); FI;
IF return code segment descriptor has L-bit = 1 and D-bit = 1
THEN #GP(selector); FI;
IF return code segment selector RPL < CPL
THEN #GP(selector); FI;
IF return code segment descriptor is conforming
and return code segment DPL > return code segment selector RPL
THEN #GP(selector); FI;
IF return code segment descriptor is non-conforming
and return code segment DPL != return code segment selector RPL
THEN #GP(selector); FI;
IF return code segment descriptor is not present
THEN #NP(selector); FI:
IF return code segment selector RPL > CPL
THEN GOTO IA-32E-MODE-RETURN-TO-OUTER-PRIVILEGE-LEVEL;
ELSE GOTO IA-32E-MODE-RETURN-SAME-PRIVILEGE-LEVEL;
FI;
FI;
IA-32E-MODE-RETURN-SAME-PRIVILEGE-LEVEL:
IF the return instruction pointer is not within the return code segment limit
THEN #GP(0); FI;
IF the return instruction pointer is not within canonical address space
THEN #GP(0); FI;
IF OperandSize = 32
THEN
EIP <- Pop();
CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded *)
ELSE
IF OperandSize = 16
THEN
EIP <- Pop();
EIP <- EIP AND 0000FFFFH;
CS <- Pop(); (* 16-bit pop *)
ELSE (* OperandSize = 64 *)
RIP <- Pop();
CS <- Pop(); (* 64-bit pop, high-order 48 bits discarded *)
FI;
FI;
IF instruction has immediate operand
THEN (* Release parameters from stack *)
IF StackAddressSize = 32
THEN
ESP <- ESP + SRC;
ELSE
IF StackAddressSize = 16
THEN
SP <- SP + SRC;
ELSE (* StackAddressSize = 64 *)
RSP <- RSP + SRC;
FI;
FI;
FI;
IA-32E-MODE-RETURN-TO-OUTER-PRIVILEGE-LEVEL:
IF top (16 + SRC) bytes of stack are not within stack limits (OperandSize = 32)
or top (8 + SRC) bytes of stack are not within stack limits (OperandSize = 16)
THEN #SS(0); FI;
IF top (16 + SRC) bytes of stack are not in canonical address space (OperandSize = 32)
or top (8 + SRC) bytes of stack are not in canonical address space (OperandSize = 16)
or top (32 + SRC) bytes of stack are not in canonical address space (OperandSize = 64)
THEN #SS(0); FI;
Read return stack segment selector;
IF stack segment selector is NULL
THEN
IF new CS descriptor L-bit = 0
THEN #GP(selector);
IF stack segment selector RPL = 3
THEN #GP(selector);
FI;
IF return stack segment descriptor is not within descriptor table limits
THEN #GP(selector); FI;
IF return stack segment descriptor is in non-canonical address space
THEN #GP(selector); FI;
Read segment descriptor pointed to by return segment selector;
IF stack segment selector RPL != RPL of the return code segment selector
or stack segment is not a writable data segment
or stack segment descriptor DPL != RPL of the return code segment selector
THEN #GP(selector); FI;
IF stack segment not present
THEN #SS(StackSegmentSelector); FI;
IF the return instruction pointer is not within the return code segment limit
THEN #GP(0); FI:
IF the return instruction pointer is not within canonical address space
THEN #GP(0); FI;
CPL <- ReturnCodeSegmentSelector(RPL);
IF OperandSize = 32
THEN
EIP <- Pop();
CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded, segment descriptor loaded *)
CS(RPL) <- CPL;
IF instruction has immediate operand
THEN (* Release parameters from called procedure's stack *)
IF StackAddressSize = 32
THEN
ESP <- ESP + SRC;
ELSE
IF StackAddressSize = 16
THEN
SP <- SP + SRC;
ELSE (* StackAddressSize = 64 *)
RSP <- RSP + SRC;
FI;
FI;
FI;
tempESP <- Pop();
tempSS <- Pop(); (* 32-bit pop, high-order 16 bits discarded, segment descriptor loaded *)
ESP <- tempESP;
SS <- tempSS;
ELSE
IF OperandSize = 16
THEN
EIP <- Pop();
EIP <- EIP AND 0000FFFFH;
CS <- Pop(); (* 16-bit pop; segment descriptor loaded *)
CS(RPL) <- CPL;
IF instruction has immediate operand
THEN (* Release parameters from called procedure's stack *)
IF StackAddressSize = 32
THEN
ESP <- ESP + SRC;
ELSE
IF StackAddressSize = 16
THEN
SP <- SP + SRC;
ELSE (* StackAddressSize = 64 *)
RSP <- RSP + SRC;
FI;
FI;
FI;
tempESP <- Pop();
tempSS <- Pop(); (* 16-bit pop; segment descriptor loaded *)
ESP <- tempESP;
SS <- tempSS;
ELSE (* OperandSize = 64 *)
RIP <- Pop();
CS <- Pop(); (* 64-bit pop; high-order 48 bits discarded; seg. descriptor loaded *)
CS(RPL) <- CPL;
IF instruction has immediate operand
THEN (* Release parameters from called procedure's stack *)
RSP <- RSP + SRC;
FI;
tempESP <- Pop();
tempSS <- Pop(); (* 64-bit pop; high-order 48 bits discarded; seg. desc. loaded *)
ESP <- tempESP;
SS <- tempSS;
FI;
FI;
FOR each of segment register (ES, FS, GS, and DS)
DO
IF segment register points to data or non-conforming code segment
and CPL > segment descriptor DPL; (* DPL in hidden part of segment register *)
THEN SegmentSelector <- 0; (* SegmentSelector invalid *)
FI;
OD;
IF instruction has immediate operand
THEN (* Release parameters from calling procedure's stack *)
IF StackAddressSize = 32
THEN
ESP <- ESP + SRC;
ELSE
IF StackAddressSize = 16
THEN
SP <- SP + SRC;
ELSE (* StackAddressSize = 64 *)
RSP <- RSP + SRC;
FI;
FI;
FI;
None.
If the RPL of the return code segment selector is less then the CPL.
If the return code or stack segment selector index is not within its descriptor table limits.
If the return code segment descriptor does not indicate a code segment.
If the return code segment is non-conforming and the segment selector's DPL is not equal to the RPL of the code segment's segment selector
If the return code segment is conforming and the segment selector's DPL greater than the RPL of the code segment's segment selector
If the stack segment is not a writable data segment.
If the stack segment selector RPL is not equal to the RPL of the return code segment selector.
If the stack segment descriptor DPL is not equal to the RPL of the return code segment selector.
Same as 64-bit mode exceptions.
If the return instruction pointer is non-canonical.
If the return instruction pointer is not within the return code segment limit.
If the stack segment selector is NULL going back to compatibility mode.
If the stack segment selector is NULL going back to CPL3 64-bit mode.
If a NULL stack segment selector RPL is not equal to CPL going back to non-CPL3 64-bit mode.
If the return code segment selector is NULL.
If the proposed segment descriptor for a code segment does not indicate it is a code segment.
If the proposed new code segment descriptor has both the D-bit and L-bit set.
If the DPL for a nonconforming-code segment is not equal to the RPL of the code segment selector.
If CPL is greater than the RPL of the code segment selector.
If the DPL of a conforming-code segment is greater than the return code segment selector RPL.
If a segment selector index is outside its descriptor table limits.
If a segment descriptor memory address is non-canonical.
If the stack segment is not a writable data segment.
If the stack segment descriptor DPL is not equal to the RPL of the return code segment selector.
If the stack segment selector RPL is not equal to the RPL of the return code segment selector.
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레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MINSS","title":"MINSS (Intel x86/64 assembly instruction)"},"monitor":{"cat_title":"MONITOR","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MONITOR","title":"MONITOR (Intel x86/64 assembly instruction)"},"mov":{"cat_title":"MOV","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MOV","title":"MOV (Intel x86/64 assembly instruction)"},"mov_1":{"cat_title":"MOV","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MOV","title":"MOV (Intel x86/64 assembly instruction)"},"mov_2":{"cat_title":"MOV","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MOV","title":"MOV (Intel x86/64 assembly instruction)"},"movapd":{"cat_title":"MOVAPD","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MOVAPD","title":"MOVAPD (Intel x86/64 assembly instruction)"},"movaps":{"cat_title":"MOVAPS","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MOVAPS","title":"MOVAPS (Intel x86/64 assembly instruction)"},"movbe":{"cat_title":"MOVBE","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MOVBE","title":"MOVBE (Intel x86/64 assembly instruction)"},"movd-movq":{"cat_title":"MOVD, MOVQ","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MOVD, MOVQ","title":"MOVD, MOVQs (Intel x86/64 assembly instruction)"},"movddup":{"cat_title":"MOVDDUP","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MOVDDUP","title":"MOVDDUP (Intel x86/64 assembly instruction)"},"movdq2q":{"cat_title":"MOVDQ2Q","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MOVDQ2Q","title":"MOVDQ2Q (Intel x86/64 assembly instruction)"},"movdqa-vmovdqa32-vmovdqa64":{"cat_title":"MOVDQA, VMOVDQA32, VMOVDQA64","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MOVDQA, VMOVDQA32, VMOVDQA64","title":"MOVDQA, VMOVDQA32, VMOVDQA64s (Intel x86/64 assembly instruction)"},"movdqu-vmovdqu8-vmovdqu16-vmovdqu32-vmovdqu64":{"cat_title":"MOVDQU, VMOVDQU8, VMOVDQU16, VMOVDQU32, VMOVDQU64","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MOVDQU, VMOVDQU8, VMOVDQU16, VMOVDQU32, VMOVDQU64","title":"MOVDQU, VMOVDQU8, VMOVDQU16, VMOVDQU32, VMOVDQU64s (Intel x86/64 assembly instruction)"},"movhlps":{"cat_title":"MOVHLPS","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MOVHLPS","title":"MOVHLPS (Intel x86/64 assembly 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레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MOVSS","title":"MOVSS (Intel x86/64 assembly instruction)"},"movsx-movsxd":{"cat_title":"MOVSX, MOVSXD","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MOVSX, MOVSXD","title":"MOVSX, MOVSXDs (Intel x86/64 assembly instruction)"},"movupd":{"cat_title":"MOVUPD","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MOVUPD","title":"MOVUPD (Intel x86/64 assembly instruction)"},"movups":{"cat_title":"MOVUPS","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MOVUPS","title":"MOVUPS (Intel x86/64 assembly instruction)"},"movzx":{"cat_title":"MOVZX","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MOVZX","title":"MOVZX (Intel x86/64 assembly instruction)"},"mpsadbw":{"cat_title":"MPSADBW","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MPSADBW","title":"MPSADBW (Intel x86/64 assembly instruction)"},"mul":{"cat_title":"MUL","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MUL","title":"MUL (Intel x86/64 assembly instruction)"},"mulpd":{"cat_title":"MULPD","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MULPD","title":"MULPD (Intel x86/64 assembly instruction)"},"mulps":{"cat_title":"MULPS","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MULPS","title":"MULPS (Intel x86/64 assembly instruction)"},"mulsd":{"cat_title":"MULSD","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MULSD","title":"MULSD (Intel x86/64 assembly instruction)"},"mulss":{"cat_title":"MULSS","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MULSS","title":"MULSS (Intel x86/64 assembly instruction)"},"mulx":{"cat_title":"MULX","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MULX","title":"MULX (Intel x86/64 assembly instruction)"},"mwait":{"cat_title":"MWAIT","path":"/X86-64 명령어 레퍼런스/M","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"MWAIT","title":"MWAIT (Intel x86/64 assembly instruction)"},"neg":{"cat_title":"NEG","path":"/X86-64 명령어 레퍼런스/N","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"NEG","title":"NEG (Intel x86/64 assembly instruction)"},"nop":{"cat_title":"NOP","path":"/X86-64 명령어 레퍼런스/N","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"NOP","title":"NOP (Intel x86/64 assembly instruction)"},"not":{"cat_title":"NOT","path":"/X86-64 명령어 레퍼런스/N","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"NOT","title":"NOT (Intel x86/64 assembly instruction)"},"or":{"cat_title":"OR","path":"/X86-64 명령어 레퍼런스/O","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"OR","title":"OR (Intel x86/64 assembly instruction)"},"orpd":{"cat_title":"ORPD","path":"/X86-64 명령어 레퍼런스/O","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"ORPD","title":"ORPD (Intel x86/64 assembly instruction)"},"orps":{"cat_title":"ORPS","path":"/X86-64 명령어 레퍼런스/O","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"ORPS","title":"ORPS (Intel x86/64 assembly instruction)"},"out":{"cat_title":"OUT","path":"/X86-64 명령어 레퍼런스/O","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"OUT","title":"OUT (Intel x86/64 assembly instruction)"},"outs-outsb-outsw-outsd":{"cat_title":"OUTS, OUTSB, OUTSW, OUTSD","path":"/X86-64 명령어 레퍼런스/O","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"OUTS, OUTSB, OUTSW, OUTSD","title":"OUTS, OUTSB, OUTSW, OUTSDs (Intel x86/64 assembly instruction)"},"pabsb-pabsw-pabsd-pabsq":{"cat_title":"PABSB, PABSW, PABSD, PABSQ","path":"/X86-64 명령어 레퍼런스/P","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"PABSB, PABSW, PABSD, PABSQ","title":"PABSB, PABSW, PABSD, PABSQs (Intel x86/64 assembly instruction)"},"packsswb-packssdw":{"cat_title":"PACKSSWB, PACKSSDW","path":"/X86-64 명령어 레퍼런스/P","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"PACKSSWB, PACKSSDW","title":"PACKSSWB, PACKSSDWs (Intel x86/64 assembly instruction)"},"packusdw":{"cat_title":"PACKUSDW","path":"/X86-64 명령어 레퍼런스/P","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"PACKUSDW","title":"PACKUSDW (Intel x86/64 assembly instruction)"},"packuswb":{"cat_title":"PACKUSWB","path":"/X86-64 명령어 레퍼런스/P","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"PACKUSWB","title":"PACKUSWB (Intel x86/64 assembly instruction)"},"paddb-paddw-paddd-paddq":{"cat_title":"PADDB, PADDW, PADDD, PADDQ","path":"/X86-64 명령어 레퍼런스/P","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"PADDB, PADDW, PADDD, PADDQ","title":"PADDB, PADDW, PADDD, PADDQs (Intel x86/64 assembly instruction)"},"paddsb-paddsw":{"cat_title":"PADDSB, PADDSW","path":"/X86-64 명령어 레퍼런스/P","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"PADDSB, PADDSW","title":"PADDSB, PADDSWs (Intel x86/64 assembly instruction)"},"paddusb-paddusw":{"cat_title":"PADDUSB, PADDUSW","path":"/X86-64 명령어 레퍼런스/P","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"PADDUSB, PADDUSW","title":"PADDUSB, PADDUSWs (Intel x86/64 assembly instruction)"},"palignr":{"cat_title":"PALIGNR","path":"/X86-64 명령어 레퍼런스/P","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"PALIGNR","title":"PALIGNR (Intel x86/64 assembly instruction)"},"pand":{"cat_title":"PAND","path":"/X86-64 명령어 레퍼런스/P","publish_date":"2020-09-01","published":"2020-09-01","ref_title":"PAND","title":"PAND (Intel x86/64 assembly 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