모두의 코드
REP, REPE, REPZ, REPNE, REPNZs (Intel x86/64 assembly instruction)

작성일 : 2020-09-01 이 글은 48 번 읽혔습니다.

REP, REPE, REPZ, REPNE, REPNZ

Repeat String Operation Prefix

참고 사항

아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.

OpcodeInstructionOp/
En
64-Bit
Mode
Compat/
Leg Mode
Description
F3 6CREP INS m8 DXNPValidValidInput (E)CX bytes from port DX into ES:[(E)DI].
F3 6CREP INS m8 DXNPValidN.E.Input RCX bytes from port DX into [RDI].
F3 6DREP INS m16 DXNPValidValidInput (E)CX words from port DX into ES:[(E)DI.]
F3 6DREP INS m32 DXNPValidValidInput (E)CX doublewords from port DX into ES:[(E)DI].
F3 6DREP INS r/m32 DXNPValidN.E.Input RCX default size from port DX into [RDI].
F3 A4REP MOVS m8 m8NPValidValidMove (E)CX bytes from DS:[(E)SI] to ES:[(E)DI].
F3 REX.W A4REP MOVS m8 m8NPValidN.E.Move RCX bytes from [RSI] to [RDI].
F3 A5REP MOVS m16 m16NPValidValidMove (E)CX words from DS:[(E)SI] to ES:[(E)DI].
F3 A5REP MOVS m32 m32NPValidValidMove (E)CX doublewords from DS:[(E)SI] to ES:[(E)DI].
F3 REX.W A5REP MOVS m64 m64NPValidN.E.Move RCX quadwords from [RSI] to [RDI].
F3 6EREP OUTS DX r/m8NPValidValidOutput (E)CX bytes from DS:[(E)SI] to port DX.
F3 REX.W 6EREP OUTS DX r/m8*NPValidN.E.Output RCX bytes from [RSI] to port DX.
F3 6FREP OUTS DX r/m16NPValidValidOutput (E)CX words from DS:[(E)SI] to port DX.
F3 6FREP OUTS DX r/m32NPValidValidOutput (E)CX doublewords from DS:[(E)SI] to port DX.
F3 REX.W 6FREP OUTS DX r/m32NPValidN.E.Output RCX default size from [RSI] to port DX.
F3 ACREP LODS ALNPValidValidLoad (E)CX bytes from DS:[(E)SI] to AL.
F3 REX.W ACREP LODS ALNPValidN.E.Load RCX bytes from [RSI] to AL.
F3 ADREP LODS AXNPValidValidLoad (E)CX words from DS:[(E)SI] to AX.
F3 ADREP LODS EAXNPValidValidLoad (E)CX doublewords from DS:[(E)SI] to EAX.
F3 REX.W ADREP LODS RAXNPValidN.E.Load RCX quadwords from [RSI] to RAX.
F3 AAREP STOS m8NPValidValidFill (E)CX bytes at ES:[(E)DI] with AL.
F3 REX.W AAREP STOS m8NPValidN.E.Fill RCX bytes at [RDI] with AL.
F3 ABREP STOS m16NPValidValidFill (E)CX words at ES:[(E)DI] with AX.
F3 ABREP STOS m32NPValidValidFill (E)CX doublewords at ES:[(E)DI] with EAX.
F3 REX.W ABREP STOS m64NPValidN.E.Fill RCX quadwords at [RDI] with RAX.
F3 A6REPE CMPS m8 m8NPValidValidFind nonmatching bytes in ES:[(E)DI] and DS:[(E)SI].
F3 REX.W A6REPE CMPS m8 m8NPValidN.E.Find non-matching bytes in [RDI] and [RSI].
F3 A7REPE CMPS m16 m16NPValidValidFind nonmatching words in ES:[(E)DI] and DS:[(E)SI].
F3 A7REPE CMPS m32 m32NPValidValidFind nonmatching doublewords in ES:[(E)DI] and DS:[(E)SI].
F3 REX.W A7REPE CMPS m64 m64NPValidN.E.Find non-matching quadwords in [RDI] and [RSI].
F3 AEREPE SCAS m8NPValidValidFind non-AL byte starting at ES:[(E)DI].
F3 REX.W AEREPE SCAS m8NPValidN.E.Find non-AL byte starting at [RDI].
F3 AFREPE SCAS m16NPValidValidFind non-AX word starting at ES:[(E)DI].
F3 AFREPE SCAS m32NPValidValidFind non-EAX doubleword starting at ES:[(E)DI].
InstructionOp/
En
64-Bit
Mode
Compat/
Leg Mode
-----------------------------------------------------------------------------------------------------
REPE SCAS m64NPValidN.E.
REPNE CMPS m8, m8NPValidValid
REPNE CMPS m8, m8NPValidN.E.
REPNE CMPS m16, m16NPValidValid
REPNE CMPS m32, m32NPValidValid
REPNE CMPS m64, m64NPValidN.E.
REPNE SCAS m8NPValidValid
REPNE SCAS m8NPValidN.E.
REPNE SCAS m16NPValidValid
REPNE SCAS m32NPValidValid
REPNE SCAS m64NPValidN.E.

Opcode Description

F3 REX.W AF Find non-RAX quadword starting at [RDI].

F2 A6 Find matching bytes in ES:[(E)DI] and DS:[(E)SI].

F2 REX.W A6 Find matching bytes in [RDI] and [RSI].

F2 A7 Find matching words in ES:[(E)DI] and DS:[(E)SI].

F2 A7 Find matching doublewords in ES:[(E)DI] and DS:[(E)SI].

F2 REX.W A7 Find matching doublewords in [RDI] and [RSI].

F2 AE Find AL, starting at ES:[(E)DI].

F2 REX.W AE Find AL, starting at [RDI].

F2 AF Find AX, starting at ES:[(E)DI].

F2 AF Find EAX, starting at ES:[(E)DI].

F2 REX.W AF Find RAX, starting at [RDI].

* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH

Instruction Operand Encoding

Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA

Description

Repeats a string instruction the number of times specified in the count register or until the indicated condition of the ZF flag is no longer met. The REP (repeat), REPE (repeat while equal), REPNE (repeat while not equal), REPZ (repeat while zero), and REPNZ (repeat while not zero) mnemonics are prefixes that can be added to one of the string instructions. The REP prefix can be added to the INS, OUTS, MOVS, LODS, and STOS instructions, and the REPE, REPNE, REPZ, and REPNZ prefixes can be added to the CMPS and SCAS instructions. (The REPZ and REPNZ prefixes are synonymous forms of the REPE and REPNE prefixes, respectively.) The F3H prefix is defined for the following instructions and undefined for the rest:

  • F3H as REP/REPE/REPZ for string and input/output instruction.

The REP prefixes apply only to one string instruction at a time. To repeat a block of instructions, use the LOOP instruction or another looping construct. All of these repeat prefixes cause the associated instruction to be repeated until the count in register is decremented to 0. See Table 4-17.

Table 4-17. Repeat Prefixes

Repeat PrefixTermination Condition 1*Termination Condition 2
REPRCX or (E)CX = 0None
REPE/REPZRCX or (E)CX = 0ZF = 0
REPNE/REPNZRCX or (E)CX = 0ZF = 1

* Count register is CX, ECX or RCX by default, depending on attributes of the operating modes.


The REPE, REPNE, REPZ, and REPNZ prefixes also check the state of the ZF flag after each iteration and terminate the repeat loop if the ZF flag is not in the specified state. When both termination conditions are tested, the cause of a repeat termination can be determined either by testing the count register with a JECXZ instruction or by testing the ZF flag (with a JZ, JNZ, or JNE instruction).
When the REPE/REPZ and REPNE/REPNZ prefixes are used, the ZF flag does not require initialization because both the CMPS and SCAS instructions affect the ZF flag according to the results of the comparisons they make.
A repeating string operation can be suspended by an exception or interrupt. When this happens, the state of the registers is preserved to allow the string operation to be resumed upon a return from the exception or interrupt handler. The source and destination registers point to the next string elements to be operated on, the EIP register points to the string instruction, and the ECX register has the value it held following the last successful iteration of the instruction. This mechanism allows long string operations to proceed without affecting the interrupt response time of the system.
When a fault occurs during the execution of a CMPS or SCAS instruction that is prefixed with REPE or REPNE, the EFLAGS value is restored to the state prior to the execution of the instruction. Since the SCAS and CMPS instruc-tions do not use EFLAGS as an input, the processor can resume the instruction after the page fault handler.
Use the REP INS and REP OUTS instructions with caution. Not all I/O ports can handle the rate at which these instructions execute. Note that a REP STOS instruction is the fastest way to initialize a large block of memory.
In 64-bit mode, the operand size of the count register is associated with the address size attribute. Thus the default count register is RCX; REX.W has no effect on the address size and the count register. In 64-bit mode, if 67H is used to override address size attribute, the count register is ECX and any implicit source/destination operand will use the corresponding 32-bit index register. See the summary chart at the beginning of this section for encoding data and limits.
REP INS may read from the I/O port without writing to the memory location if an exception or VM exit occurs due to the write (e.g. #PF). If this would be problematic, for example because the I/O port read has side-effects, soft-ware should ensure the write to the memory location does not cause an exception or VM exit

Operation

IF AddressSize = 16
    THEN
        Use CX for CountReg;
        Implicit Source/Dest operand for memory use of SI/DI;
    ELSE IF AddressSize = 64
        THEN Use RCX for CountReg; 
        Implicit Source/Dest operand for memory use of RSI/RDI;
    ELSE
        Use ECX for CountReg;
        Implicit Source/Dest operand for memory use of ESI/EDI;
FI;
WHILE CountReg != 0
    DO
          Service pending interrupts (if any);
          Execute associated string instruction;
          CountReg <- (CountReg - 1);
          IF CountReg = 0
                THEN exit WHILE loop; FI;
          IF (Repeat prefix is REPZ or REPE) and (ZF = 0)
          or (Repeat prefix is REPNZ or REPNE) and (ZF = 1)
                THEN exit WHILE loop; FI;OD;

Flags Affected

None; however, the CMPS and SCAS instructions do set the status flags in the EFLAGS register.

Exceptions (All Operating Modes)

Exceptions may be generated by an instruction associated with the prefix.

64-Bit Mode Exceptions

#GP(0)

  • If the memory address is in a non-canonical form.

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