모두의 코드
VPCMPW, VPCMPUWs (Intel x86/64 assembly instruction)
VPCMPW, VPCMPUW
Compare Packed Word Values Into Mask
참고 사항
아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.
Opcode/ | Op/ | 64/32 | CPUID | Description |
|---|---|---|---|---|
| FVM | V/V | AVX512VL | Compare packed signed word integers in xmm3/m128 and xmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. |
| FVM | V/V | AVX512VL | Compare packed signed word integers in ymm3/m256 and ymm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. |
| FVM | V/V | AVX512BW | Compare packed signed word integers in zmm3/m512 and zmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. |
| FVM | V/V | AVX512VL | Compare packed unsigned word integers in xmm3/m128 and xmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. |
| FVM | V/V | AVX512VL | Compare packed unsigned word integers in ymm3/m256 and ymm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. |
| FVM | V/V | AVX512BW | Compare packed unsigned word integers in zmm3/m512 and zmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. |
Instruction Operand Encoding
Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|
FVM | ModRM:reg (w) | vvvv (r) | ModRM:r/m (r) | NA |
Description
Performs a SIMD compare of the packed integer word in the second source operand and the first source operand and returns the results of the comparison to the mask destination operand. The comparison predicate operand (immediate byte) specifies the type of comparison performed on each pair of packed values in the two source oper-ands. The result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).
VPCMPW performs a comparison between pairs of signed word values.
VPCMPUW performs a comparison between pairs of unsigned word values.
The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand (first operand) is a mask register k1. Up to 32/16/8 comparisons are performed with results written to the destination operand under the writemask k2.
The comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed. Bits 3 through 7 of the immediate are reserved. Compiler can implement the pseudo-op mnemonic listed in Table 5-10.
Operation
VPCMPW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
i <- j * 16
IF k2[j] OR *no writemask*
THEN
ICMP <- SRC1[i+15:i] OP SRC2[i+15:i];
IF CMP = TRUE
THEN DEST[j] <- 1;
ELSE DEST[j] <- 0; FI;
ELSE DEST[j] = 0 ; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0
VPCMPUW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
i <- j * 16
IF k2[j] OR *no writemask*
THEN
CMP <- SRC1[i+15:i] OP SRC2[i+15:i];
IF CMP = TRUE
THEN DEST[j] <- 1;
ELSE DEST[j] <- 0; FI;
ELSE DEST[j] = 0 ; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0
Intel C/C++ Compiler Intrinsic Equivalent
VPCMPW __mmask32 _mm512_cmp_epi16_mask(__m512i a, __m512i b, int cmp); VPCMPW __mmask32 _mm512_mask_cmp_epi16_mask(__mmask32 m, __m512i a, __m512i b, int cmp); VPCMPW __mmask16 _mm256_cmp_epi16_mask(__m256i a, __m256i b, int cmp); VPCMPW __mmask16 _mm256_mask_cmp_epi16_mask(__mmask16 m, __m256i a, __m256i b, int cmp); VPCMPW __mmask8 _mm_cmp_epi16_mask(__m128i a, __m128i b, int cmp); VPCMPW __mmask8 _mm_mask_cmp_epi16_mask(__mmask8 m, __m128i a, __m128i b, int cmp); VPCMPW __mmask32 _mm512_cmp[eq | ge | gt | le | lt | neq] _epi16_mask(__m512i a, __m512i b); VPCMPW __mmask32 _mm512_mask_cmp[eq | ge | gt | le | lt | neq] _epi16_mask( __mmask32 m, __m512i a, __m512i b); VPCMPW __mmask16 _mm256_cmp[eq | ge | gt | le | lt | neq] _epi16_mask(__m256i a, __m256i b); VPCMPW __mmask16 _mm256_mask_cmp[eq | ge | gt | le | lt | neq] _epi16_mask( __mmask16 m, __m256i a, __m256i b); VPCMPW __mmask8 _mm_cmp[eq | ge | gt | le | lt | neq] _epi16_mask(__m128i a, __m128i b); VPCMPW __mmask8 _mm_mask_cmp[eq | ge | gt | le | lt | neq] _epi16_mask( __mmask8 m, __m128i a, __m128i b); VPCMPUW __mmask32 _mm512_cmp_epu16_mask(__m512i a, __m512i b, int cmp); VPCMPUW __mmask32 _mm512_mask_cmp_epu16_mask(__mmask32 m, __m512i a, __m512i b, int cmp); VPCMPUW __mmask16 _mm256_cmp_epu16_mask(__m256i a, __m256i b, int cmp); VPCMPUW __mmask16 _mm256_mask_cmp_epu16_mask(__mmask16 m, __m256i a, __m256i b, int cmp); VPCMPUW __mmask8 _mm_cmp_epu16_mask(__m128i a, __m128i b, int cmp); VPCMPUW __mmask8 _mm_mask_cmp_epu16_mask(__mmask8 m, __m128i a, __m128i b, int cmp); VPCMPUW __mmask32 _mm512_cmp[eq | ge | gt | le | lt | neq] _epu16_mask( __m512i a, __m512i b, int cmp); VPCMPUW __mmask32 _mm512_mask_cmp[eq | ge | gt | le | lt | neq] _epu16_mask( __mmask32 m, __m512i a, __m512i b, int cmp); VPCMPUW __mmask16 _mm256_cmp[eq | ge | gt | le | lt | neq] _epu16_mask( __m256i a, __m256i b, int cmp); VPCMPUW __mmask16 _mm256_mask_cmp[eq | ge | gt | le | lt | neq] _epu16_mask( __mmask16 m, __m256i a, __m256i b, int cmp); VPCMPUW __mmask8 _mm_cmp[eq | ge | gt | le | lt | neq] _epu16_mask(__m128i a, __m128i b, int cmp); VPCMPUW __mmask8 _mm_mask_cmp[eq | ge | gt | le | lt | neq] _epu16_mask( __mmask8 m, __m128i a, __m128i b, int cmp);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb.
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