모두의 코드
VPCOMPRESSQ (Intel x86/64 assembly instruction)
VPCOMPRESSQ
Store Sparse Packed Quadword Integer Values into Dense Memory/Register
참고 사항
아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.
Opcode/ | Op/ | 64/32 | CPUID | Description |
|---|---|---|---|---|
| T1S | V/V | AVX512VL | Compress packed quadword integer values from xmm2 to xmm1/m128 using controlmask k1. |
| T1S | V/V | AVX512VL | Compress packed quadword integer values from ymm2 to ymm1/m256 using controlmask k1. |
| T1S | V/V | AVX512F | Compress packed quadword integer values from zmm2 to zmm1/m512 using controlmask k1. |
Instruction Operand Encoding
Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|
T1S | ModRM:r/m (w) | ModRM:reg (r) | NA | NA |
Description
Compress (stores) up to 8/4/2 quadword integer values from the source operand (second operand) to the destina-tion operand (first operand). The source operand is a ZMM/YMM/XMM register, the destination operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The opmask register k1 selects the active elements (partial vector or possibly non-contiguous if less than 8 active elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to the destination starting from the low element of the destination operand.
Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z must be zero.
Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper bits are zeroed.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element instead of the size of the full vector.
Operation
VPCOMPRESSQ (EVEX encoded versions) store form
(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE <-!= 64
k <- 0
FOR j <- 0 TO KL-1
i <- j * 64
IF k1[j] OR *no controlmask*
THEN
DEST[k+SIZE-1:k]<- SRC[i+63:i]
k <- k + SIZE
FI;
ENFOR
VPCOMPRESSQ (EVEX encoded versions) reg-reg form
(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE <-!= 64
k <- 0
FOR j <- 0 TO KL-1
i <- j * 64
IF k1[j] OR *no controlmask*
THEN
DEST[k+SIZE-1:k]<- SRC[i+63:i]
k <- k + SIZE
FI;
ENDFOR
IF *merging-masking*
THEN *DEST[VL-1:k] remains unchanged*
ELSE DEST[VL-1:k] <- 0
FI
DEST[MAX_VL-1:VL] <- 0
Intel C/C++ Compiler Intrinsic Equivalent
VPCOMPRESSQ __m512i _mm512_mask_compress_epi64(__m512i s, __mmask8 c, __m512i a); VPCOMPRESSQ __m512i _mm512_maskz_compress_epi64(__mmask8 c, __m512i a); VPCOMPRESSQ void _mm512_mask_compressstoreu_epi64(void* a, __mmask8 c, __m512i s); VPCOMPRESSQ __m256i _mm256_mask_compress_epi64(__m256i s, __mmask8 c, __m256i a); VPCOMPRESSQ __m256i _mm256_maskz_compress_epi64(__mmask8 c, __m256i a); VPCOMPRESSQ void _mm256_mask_compressstoreu_epi64(void* a, __mmask8 c, __m256i s); VPCOMPRESSQ __m128i _mm_mask_compress_epi64(__m128i s, __mmask8 c, __m128i a); VPCOMPRESSQ __m128i _mm_maskz_compress_epi64(__mmask8 c, __m128i a); VPCOMPRESSQ void _mm_mask_compressstoreu_epi64(void* a, __mmask8 c, __m128i s);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb.
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