모두의 코드
VPMOVQB, VPMOVSQB, VPMOVUSQBs (Intel x86/64 assembly instruction)
VPMOVQB, VPMOVSQB, VPMOVUSQB
Down Convert QWord to Byte
참고 사항
아래 표를 해석하는 방법은 x86-64 명령어 레퍼런스 읽는 법 글을 참조하시기 바랍니다.
Opcode/ | Op / | 64/32 | CPUID | Description |
---|---|---|---|---|
| OVM | V/V | AVX512VL | Converts 2 packed quad-word integers from xmm2 into 2 packed byte integers in xmm1/m16 with truncation under writemask k1. |
| OVM | V/V | AVX512VL | Converts 2 packed signed quad-word integers from xmm2 into 2 packed signed byte integers in xmm1/m16 using signed saturation under writemask k1. |
| OVM | V/V | AVX512VL | Converts 2 packed unsigned quad-word integers from xmm2 into 2 packed unsigned byte integers in xmm1/m16 using unsigned saturation under writemask k1. |
| OVM | V/V | AVX512VL | Converts 4 packed quad-word integers from ymm2 into 4 packed byte integers in xmm1/m32 with truncation under writemask k1. |
| OVM | V/V | AVX512VL | Converts 4 packed signed quad-word integers from ymm2 into 4 packed signed byte integers in xmm1/m32 using signed saturation under writemask k1. |
| OVM | V/V | AVX512VL | Converts 4 packed unsigned quad-word integers from ymm2 into 4 packed unsigned byte integers in xmm1/m32 using unsigned saturation under writemask k1. |
| OVM | V/V | AVX512F | Converts 8 packed quad-word integers from zmm2 into 8 packed byte integers in xmm1/m64 with truncation under writemask k1. |
| OVM | V/V | AVX512F | Converts 8 packed signed quad-word integers from zmm2 into 8 packed signed byte integers in xmm1/m64 using signed saturation under writemask k1. |
| OVM | V/V | AVX512F | Converts 8 packed unsigned quad-word integers from zmm2 into 8 packed unsigned byte integers in xmm1/m64 using unsigned saturation under writemask k1. |
Instruction Operand Encoding
Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
---|---|---|---|---|
OVM | ModRM:r/m (w) | ModRM:reg (r) | NA | NA |
Description
VPMOVQB down converts 64-bit integer elements in the source operand (the second operand) into packed byte elements using truncation. VPMOVSQB converts signed 64-bit integers into packed signed bytes using signed satu-ration. VPMOVUSQB convert unsigned quad-word values into unsigned byte values using unsigned saturation. The source operand is a vector register. The destination operand is an XMM register or a memory location.
Down-converted byte elements are written to the destination operand (the first operand) from the least-significant byte. Byte elements of the destination operand are updated according to the writemask. Bits (MAX_VL-1:64) of the destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VPMOVQB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512) FOR j <- 0 TO KL-1 i <- j * 8 m <- j * 64 IF k1[j] OR *no writemask* THEN DEST[i+7:i] <- TruncateQuadWordToByte (SRC[m+63:m]) ELSE IF *merging-masking* ; merging-masking THEN *DEST[i+7:i] remains unchanged* ELSE *zeroing-masking* ; zeroing-masking DEST[i+7:i] <- 0 FI FI; ENDFOR DEST[MAX_VL-1:VL/8] <- 0;
VPMOVQB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512) FOR j <- 0 TO KL-1 i <- j * 8 m <- j * 64 IF k1[j] OR *no writemask* THEN DEST[i+7:i] <- TruncateQuadWordToByte (SRC[m+63:m]) ELSE *DEST[i+7:i] remains unchanged* ; merging-masking FI; ENDFOR
VPMOVSQB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512) FOR j <- 0 TO KL-1 i <- j * 8 m <- j * 64 IF k1[j] OR *no writemask* THEN DEST[i+7:i] <- SaturateSignedQuadWordToByte (SRC[m+63:m]) ELSE IF *merging-masking* ; merging-masking THEN *DEST[i+7:i] remains unchanged* ELSE *zeroing-masking* ; zeroing-masking DEST[i+7:i] <- 0 FI FI; ENDFOR DEST[MAX_VL-1:VL/8] <- 0;
VPMOVSQB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512) FOR j <- 0 TO KL-1 i <- j * 8 m <- j * 64 IF k1[j] OR *no writemask* THEN DEST[i+7:i] <- SaturateSignedQuadWordToByte (SRC[m+63:m]) ELSE *DEST[i+7:i] remains unchanged* ; merging-masking FI; ENDFOR
VPMOVUSQB instruction (EVEX encoded versions) when dest is a register
(KL, VL) = (2, 128), (4, 256), (8, 512) FOR j <- 0 TO KL-1 i <- j * 8 m <- j * 64 IF k1[j] OR *no writemask* THEN DEST[i+7:i] <- SaturateUnsignedQuadWordToByte (SRC[m+63:m]) ELSE IF *merging-masking* ; merging-masking THEN *DEST[i+7:i] remains unchanged* ELSE *zeroing-masking* ; zeroing-masking DEST[i+7:i] <- 0 FI FI; ENDFOR DEST[MAX_VL-1:VL/8] <- 0;
VPMOVUSQB instruction (EVEX encoded versions) when dest is memory
(KL, VL) = (2, 128), (4, 256), (8, 512) FOR j <- 0 TO KL-1 i <- j * 8 m <- j * 64 IF k1[j] OR *no writemask* THEN DEST[i+7:i] <- SaturateUnsignedQuadWordToByte (SRC[m+63:m]) ELSE *DEST[i+7:i] remains unchanged* ; merging-masking FI; ENDFOR
Intel C/C++ Compiler Intrinsic Equivalents
VPMOVQB __m128i _mm512_cvtepi64_epi8(__m512i a); VPMOVQB __m128i _mm512_mask_cvtepi64_epi8(__m128i s, __mmask8 k, __m512i a); VPMOVQB __m128i _mm512_maskz_cvtepi64_epi8(__mmask8 k, __m512i a); VPMOVQB void _mm512_mask_cvtepi64_storeu_epi8(void* d, __mmask8 k, __m512i a); VPMOVSQB __m128i _mm512_cvtsepi64_epi8(__m512i a); VPMOVSQB __m128i _mm512_mask_cvtsepi64_epi8(__m128i s, __mmask8 k, __m512i a); VPMOVSQB __m128i _mm512_maskz_cvtsepi64_epi8(__mmask8 k, __m512i a); VPMOVSQB void _mm512_mask_cvtsepi64_storeu_epi8(void* d, __mmask8 k, __m512i a); VPMOVUSQB __m128i _mm512_cvtusepi64_epi8(__m512i a); VPMOVUSQB __m128i _mm512_mask_cvtusepi64_epi8(__m128i s, __mmask8 k, __m512i a); VPMOVUSQB __m128i _mm512_maskz_cvtusepi64_epi8(__mmask8 k, __m512i a); VPMOVUSQB void _mm512_mask_cvtusepi64_storeu_epi8(void* d, __mmask8 k, __m512i a); VPMOVUSQB __m128i _mm256_cvtusepi64_epi8(__m256i a); VPMOVUSQB __m128i _mm256_mask_cvtusepi64_epi8(__m128i a, __mmask8 k, __m256i b); VPMOVUSQB __m128i _mm256_maskz_cvtusepi64_epi8(__mmask8 k, __m256i b); VPMOVUSQB void _mm256_mask_cvtusepi64_storeu_epi8(void*, __mmask8 k, __m256i b); VPMOVUSQB __m128i _mm_cvtusepi64_epi8(__m128i a); VPMOVUSQB __m128i _mm_mask_cvtusepi64_epi8(__m128i a, __mmask8 k, __m128i b); VPMOVUSQB __m128i _mm_maskz_cvtusepi64_epi8(__mmask8 k, __m128i b); VPMOVUSQB void _mm_mask_cvtusepi64_storeu_epi8(void*, __mmask8 k, __m128i b); VPMOVSQB __m128i _mm256_cvtsepi64_epi8(__m256i a); VPMOVSQB __m128i _mm256_mask_cvtsepi64_epi8(__m128i a, __mmask8 k, __m256i b); VPMOVSQB __m128i _mm256_maskz_cvtsepi64_epi8(__mmask8 k, __m256i b); VPMOVSQB void _mm256_mask_cvtsepi64_storeu_epi8(void*, __mmask8 k, __m256i b); VPMOVSQB __m128i _mm_cvtsepi64_epi8(__m128i a); VPMOVSQB __m128i _mm_mask_cvtsepi64_epi8(__m128i a, __mmask8 k, __m128i b); VPMOVSQB __m128i _mm_maskz_cvtsepi64_epi8(__mmask8 k, __m128i b); VPMOVSQB void _mm_mask_cvtsepi64_storeu_epi8(void*, __mmask8 k, __m128i b); VPMOVQB __m128i _mm256_cvtepi64_epi8(__m256i a); VPMOVQB __m128i _mm256_mask_cvtepi64_epi8(__m128i a, __mmask8 k, __m256i b); VPMOVQB __m128i _mm256_maskz_cvtepi64_epi8(__mmask8 k, __m256i b); VPMOVQB void _mm256_mask_cvtepi64_storeu_epi8(void*, __mmask8 k, __m256i b); VPMOVQB __m128i _mm_cvtepi64_epi8(__m128i a); VPMOVQB __m128i _mm_mask_cvtepi64_epi8(__m128i a, __mmask8 k, __m128i b); VPMOVQB __m128i _mm_maskz_cvtepi64_epi8(__mmask8 k, __m128i b); VPMOVQB void _mm_mask_cvtepi64_storeu_epi8(void*, __mmask8 k, __m128i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E6.
#UD If EVEX.vvvv != 1111B.
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